Four primary aspects of chip design are processor, memory, IO, and communication. Communication amalgamated over a SoC (system-on-chip) is the basis of origin of an NoC (network-on-chip). Continuous increase in processing/communication needs with the rapid growth in VLSI industry providing higher and higher integration density within a single die has boosted the step towards this new paradigm s...

Nowadays System-On-Chips (SoCs) have evolved considerably in term of performances, reliability and integration capacity. The last advantage has induced the growth of the number of cores or Intellectual Properties (IPs) in a same chip. Unfortunately, this important number of IPs has caused a new issue which is the intra-communication between the elements of a same chip. To resolve this problem, ...

With the progress of deep submicron technology power consumption and temperature related issues have become two of the most critical aspects for chip design. Therefore, very large-scale integrated systems like Systems-on-Chip (SoCs) are exposed to an ever increasing thermal stress. This necessitates effective mechanisms for thermal management. In this paper we propose to precompute and proactiv...

Optical network-on-chip (ONoC) has been proposed to provide higher bandwidth and lower power consumption for future multicore systems. However, due to the intrinsic characteristic of optical devices, crosstalk noise is a potential issue for ONoC. The traditional routing algorithms for Benes ONoC have not considered the aspect of crosstalk. In this paper, we build the crosstalk model of the opti...

Network-on-Chip (NoC) has been proposed as an alternative to bus-based schemes to achieve high performance and scalability in System-on-Chip (SoC) design. Performance evaluation of On-Chip Interconnect (OCI) architectures is widely based on simulation which becomes computationally expensive, especially for largescale NoCs. In this paper, we study

The idea of using on chip packet switched networks for interconnecting a large number of IP cores is very practical for designing complex SoCs since it gives possibility of not only reusing IP cores but also the interconnection infrastructure. However, the real effort and time in using these Networks on Chip (NoC) goes in developing interfaces for connecting cores to the on-chip network. Standa...

The Network-on-Chip (NoC) paradigm has been herald as the solution to the communication limitation that System-On-Chip (SoC) poses. However, power Consumption is one of its major defects. To ensure that a high performance architecture is constructed, analyzing how power can be reduced in each area of the network is essential. Power dissipation can be reduced by adjustments to the routers, the a...

Hybrid wired/wireless on-chip network is a promising communication architecture for multi-/many-core SoC. For applicationspecific SoC design, it is important to design a dedicated on-chip network architecture according to the application-specific nature. In this paper, we propose a heuristic wireless link allocation algorithm for creating hybrid on-chip network architecture. The algorithm can e...

Network-on-Chip (NoC) has been proposed as an attractive alternative to traditional dedicated busses in order to achieve modularity and high performance in the future System-on-Chip (SoC) designs. Recently, endto-end congestion control has gained popularity in the design process of network-on-chip based SoCs. This paper addresses a congestion control scenario under traffic mixture which is comp...