Modifying the sense strand of nuclease-resistant siRNA with 3'-cholesterol (Chol-*siRNA) increases mRNA suppression after i.v. administration but with relatively low efficacy. We previously found evidence in vitro that suggests complexation of Chol-siRNA with PLL-PEG(5K), a block copolymer of poly-l-lysine and 5 kDa polyethylene glycol, may increase the efficacy of Chol-siRNA in vivo in a PLL b...

STUDY DESIGN Retrospective review. OBJECTIVE To evaluate key risk factors for the development of C5 palsy after cervical corpectomy, including resection of the posterior longitudinal ligament (PLL). SUMMARY OF BACKGROUND DATA Postoperative C5 palsy is a well-known complication after cervical spine surgery. It is unknown whether resection of the PLL affects the incidence of C5 palsy. METHO...

A fully integrated phase-locked loop (PLL) fabricated in a 0.24 micrometer, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chip. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24 micrometer CMOS technology. Also it has very low peak-to-peak ...

A conjugate of horseradish peroxidase (HRP) to poly(L-lysine) (PLL) was used as a non-specific adsorptive probe to study transcytosis in MDCK strain I and Caco-2 epithelial cells. As we have shown previously, HRP-PLL transcytosis proceeds via an intracellular, non-lysosomal proteolytic compartment in MDCK cells; yet, this compartment is utilized for transcytosis only in the basal-to-apical dire...

We used 204 nm excitation UV Resonance Raman (UVRR) spectroscopy to examine the effects of NaClO(4) on the conformation of poly-L-lysine (PLL). The presence of NaClO(4) induces the formation of α-helix, π-helix/bulge, and turn conformations. The dependence of the AmIII(3) frequency on the peptide Ψ Ramachandran angle allows us to experimentally determine the conformational population distributi...

This work presents a method for modeling and simulating a second-order analog phase-locked loops (PLL) in time domain for studying its acquisition behavior. The proposed method uses phase error process for analyzing the PLL characteristics. The method enables to study the lockin and pull-in phenomena of analog PLL and the effects of changing phase offset and voltage offset values on acquisition...

This paper describes the design and implementation of a current-mode phase-locked loop (PLL) using static and dynamic (log-domain) translinear circuits. The loop is fully tuneable, with independent control of center frequency and loop bandwidth. The loop employs a recently proposed current-mode “log-domain” oscillator in a classical PLL topology to obtain these features. The PLL has been fabric...

A digital decision-directed phase-locked loop (PLL) for use in optical pulse code-division multiple-access (CDMA) systems based on coherent correlation demodulation is proposed. PLL performance is affected by multiuser interference, laser phase noise and optical shot noise. The effect of these sources of interference and noise on PLL performance is evaluated based on a nonlinear model (the Fokk...

This paper proposes a 60GHz quadrature PLL frequency synthesizer that has a tuning range capable of covering the whole band specified by the IEEE802.15.3c with exceptional phase noise. The synthesizer is constructed using a 20GHz PLL that is coupled with a frequency tripler to generate the 60GHz signal. The 20GHz PLL generates a signal with a phase noise as low as −106dBc/Hz using tail feedback...

Phase-locked loops (PLL) are widely used in the synchronization of grid interfaced power converters. One solution is based on orthogonal signal generation (OSG), which requires frequency information for their appropriate operation. This article developed a new to achieve PLL function single-phase interconnection but eradicate additional feedback traditional architecture all-pass filter (APF-PLL...