A computer program has been written to investigate the design tradeoffs of high frequency diode frequency multipliers. Velocity saturation and breakdown have been included in a device model that is part of a nonlinear multiple reflection simulation. The device doping, epitaxial layer length and velocity vs. electric field curve are input parameters. The program has a search routine to match the...

Joint modelling of fiscal and monetary policies should elucidate on their interaction. We estimate a large parsimonious structural vector equilibrium correction model (PSVECM) to analyse the dynamics of eight variables from the US economy. Shocks to fiscal and monetary variables reveal interesting observations, with the results broadly in agreement with economic theory. A shock to only governme...

We present the formal verification of a low-power x86 floating-point multiplier. The multiplier operates iteratively and feeds back intermediate results in redundant representation. It supports x87 and SSE instructions in various precisions and can block the issuing of new instructions. The design has been optimized for low-power operation and has not been constrained by the formal verification...

In this paper we consider three embeddings (one-parametric optimization problems) motivated by penalty, exact penalty and Lagrange multiplier methods. We give an answer to the question under which conditions these methods are successful with an arbitrarily chosen starting point. Using the theory of one-parametric optimization (the local structure of the set of stationary points and of the set o...

This work uses a partially redundant number system as an internal format for floating point arithmetic operations. The redundant number system enables carry free arithmetic operations to improve performance. Conversion from the proposed internal format back to the standard IEEE format is done only when an operand is written to memory. A detailed discussion of an adder using the proposed format ...

The floating-point unit of a S/390 CMOS microprocessor is described. It contains a 116 bit fraction dataflow for addition and subtraction and a 64 bit-wide multiplier. Besides the register array, there are no other dataflow macros used; it is fully designed with standard cell books and is placed flat with a timing driven placement algorithm. This design method allows more ’irregular’ structures...

This paper describes synthesizable VDHL implementation of elliptic curve Point Multiplication. Elliptic curves used for ECC are defined over mathematical structures called Galois fields. Based on the theory of ECC, this paper has carried out Modular addition/subtraction, EC Point doubling/addition, Modular multiplicative inversion, EC point multiplier, projective to affine coordinates conversio...

let $g$ be a $p$-group of nilpotency class $k$ with finite exponent $exp(g)$ and let $m=lfloorlog_pk floor$. we show that $exp(m^{(c)}(g))$ divides $exp(g)p^{m(k-1)}$, for all $cgeq1$, where $m^{(c)}(g)$ denotes the c-nilpotent multiplier of $g$. this implies that $exp( m(g))$ divides $exp(g)$, for all finite $p$-groups of class at most $p-1$. moreover, we show that our result is an improvement...