This paper presents a hardware design of high throughput, low latency preamble detector for 3GPP LTE physical random access channel (PRACH) receiver. The presented PRACH receiver uses the pipelined structure to improve the throughput of power delay profile (PDP) generation which is executed multiple times during the preamble detection. In addition, to reduce detection latency, we propose an ins...

In this paper we present different configurations of static ULV NP domino carry gates using precharge and pass transistor logic. The proposed ULV domino carry gates are aimed for high speed serial adders in ultra low-voltage applications. In terms of frequency, speed, PDP and EDP, the ULV carry gates offers significant improvement compared to conventional CMOS carry gate. At Minimum Energy Poin...

As embedded and portable systems were emerged power consumption of circuits had been major challenge. On the other hand latency as determines frequency of circuits is also vital task. Therefore, trade off between both of them will be desirable. Modulo adders are important part of the residue number system (RNS) based arithmetic units with the interesting moduli set , , . In this manuscript we h...

In this paper we propose a methodology to design high-speed, power-efficient static frequency dividers based on the low-voltage Folded MOS Current Mode Logic (FMCML) approach. A modeling strategy analyze dependence of propagation delay and power consumption bias currents divide-by-2 (DIV2) cell is introduced. We demonstrate that behavior FMCML DIV2 different both from one conventional MCML DFF ...

The adder circuit is basic component of arithmetic logic design and that the most important block processor architecture. Moreover, power consumption main concern for real-time digital systems. In recent times, carbon nanotube field effect transistors (CNTFET) used designs with high performance. A creative substitute highspeed, less power, small size in area CNTFET. This paper presents 1- bit f...

This paper presents a comparative research of low-power and high-speed full adder cells which are based on XOR-XNOR algorithm. The adder cells are decomposed into small modules and all of them have an in-depth analysis. Several designs of each of them are implemented, optimized, simulated and analyzed separately. We also design a novel XORXNOR module built upon bootstrapped pass transistor logi...

A new three dimensional (3D) ray-tracing propagation prediction tool (3D MRT-1) is being developed for characterisation of wideband mobile radio channel. It calculates the amplitude, phase, angle-of-departure (AOD), angle-of-arrival (AOA), optical path length and received field strength for each valid reflected or diffracted ray path. It also constructs the power delay profile (PDP) and extract...

The use of IoT technology in several applications is hampered by security and privacy concerns with edge nodes. Security flaws can only be resolved implementing cryptographic protocols on these resource constraints the nodes make it extremely difficult to implement protocols. majority protocols’ fundamental operation finite-field multiplication, their performance significantly impacted effectiv...

In this article, two soft error tolerant SRAM cells, the so-called RATF1 and RATF2, are proposed and evaluated. The proposed radiation hardened SRAM cells are capable of fully tolerating single event upsets (SEUs). Moreover, they show a high degree of robustness against single event multiple upsets (SEMUs). Over the previous SRAM cells, RATF1 and RATF2 offer lower area and power overhead. The H...

In this position paper we discuss the application of personalization in persuasive technology design in light of the Personalized Design Process model (PDP-model). The PDP-model defines personalization as aligning a persuasive product to the end-user by stakeholder involvement (i.e. designers, endusers, domain experts and family/relatives) across the Problem Definition-, the Product Designand/o...