The CMOS PLL based Frequency Synthesizer is a vital role in Receiver front end Sub component. The main objective of this paper is to design a high frequency of oscillation, less phase noise and power efficient PLL. In general, the PLL contains PFD, Loop Filter, VCO and Frequency Divider. The VCO is a critical component in Phase Locked Loop for low power CMOS designs. Here the Source Coupled VCO...

We present a scalable high-speed divide-by-N frequency divider using only basic digital CMOS circuits. The divider achieves high-speed operation using a novel parallel counter and a pipelined architecture. The parallel counter is based on a state look-ahead component in conjunction with an internal pipeline structure in order to simultaneously trigger all state value updates without a rippling ...

Received Feb 14, 2017 Revised Jun 1, 2017 Accepted Aug 11, 2017 Design and simulation for reconfigurable Wilkinson Power Divider (WPD) related to WiMAX application is proposed in this paper. This proposed design relates to dual band WiMAX frequencies at 2.5 GHz and 3.5 GHz. The main purpose of this design is to design a switchable feeding network that can cover the WiMAX standards by reconfigur...

This work proposes a substrate integrated waveguide (SIW) power divider employing the Wilkinson configuration for improving the isolation performance of conventional T-junction SIW power dividers. Measurement results at 15GHz show that the isolation (S23, S32) between output ports is about 17 dB and the output return losses (S22, S33) are about 14.5 dB, respectively. The Wilkinson-type performa...

Addressing the need for passive magneto-inductive components, a lumped-element symmetric power divider has been designed and realised for a magneto-inductive cable with the resonant frequency of 95 MHz and the passband between 73 and 174 MHz. In agreement with the theory, the measured coupling loss is 6 dB for most of the passband independent of the input port. Having proved useful for magneto-...

This letter proposed a new Wilkinson power combiner/divider (PCD) with enhanced average power-handling capability (APHC) by decreasing the impedance of microstrip combine port. For verification, one example PCD operating at 2.3GHz was designed, fabricated and measured to verify theory. One traditional also compare APHC PCD, means measuring temperature variation line same input power. The measur...

This paper presents a 0.13μm CMOS 1.7GHz VCO with frequency divider, suitable for ultra-low-power hearing-aid applications. The circuit has a 16% tuning range, a minimum power consumption of 320μW from a 0.8V power supply, power-supply and temperature compensation, an excellent 188dBc/Hz gure-of-merit without the need of off-chip components, and an area of 0.2mm.