In this paper, a new system for the instruction level timing analysis of hard real-time programs is presented. The analysis exploits the very simple structure of these programs, resulting in a considerable processing time improvement compared to general-case analysis techniques. The new analysis system covers all speed-up mechanisms used for modern superscalar processors at once: pipelining, da...

A theoretical memory with limited processing power and internal connectivity at each element is proposed. This memory carries out parallel processing within itself to solve generic array problems. The applicability of this in-memory finest-grain massive SIMD approach is studied in some details. For an array of N items, it reduces the total instruction cycle count of universal operations such as...

Instructions play an important role in everyday communication, e.g. in task-oriented dialogs. Based on a (psycho-)linguistic theoretical background, which classifies instructions as requests, we conducted experiments using a cross-modal experimental design in combination with a reaction time paradigm in order to get insights in human instruction processing. We concentrated on the interpretation...

The Cell BE architecture consists of a 64-bit Power-compliant Processing Element (PPE) and eight Synergistic Processing Elements (SPEs), loosely coupled through a coherent memory sub-system. Through their programmability, the SPEs provide computational density advantage over conventional processors while still providing greater flexibility than traditional fixed function ASICs. The SPEs' instru...

The Motorola DSP56001 is a state-of-the-art digital signal processing chip that can execute (with the clock at 25 MHz) 12.5 million instructions per second and, in a single instruction, can perform a 24 by 24-bit multiply, a 48 plus 56-bit addition, two parallel data moves, an instruction fetch and decode, and two general index updates. The 24-bit data paths and computational architecture make ...

An ultra-low-power networking protocol handling platform is urgently required to realize sustainable ad hoc communication over battery-operated devices in emergent situations without connectivity to the wired network infrastructure. In this paper, the data-driven principle is fully exploited as a basis of ultra-low power because of its on-demand control by which circuits are activated only for ...

Continuing advances in semiconductor technology and demand for higher performance will lead to more powerful, superpipelined and wider issue processors. Instruction caches in such processors will consume a significant fraction of the on-chip energy due to very wide fetch on each cycle. This paper proposes a new energy-effective design of the fetch unit that exploits the fact that not all instru...