In complex reconfigurable SoCs, the dynamism of applications requires an efficient management of the platform. To allow run-time allocation of resources, operating systems and reconfigurable SoC platforms should be developed together. The operating system requires hardware support from the platform to abstract the reconfigurable resources and to provide an efficient communication layer. This pa...

Partial reconfiguration allows for mapping and executing several tasks on an FPGA during runtime. Multitasking on FPGAs rises a number of questions on the management of the reconfigurable resource, which leads to concepts of reconfigurable operating systems. This paper focuses on a major aspect of a reconfigurable operating system: task placement and transformation. We first discuss task charac...

A polarimetry system for solar astronomy is presented. The system is based on a reconfigurable coprocessor attached to a conventional workstation. Although the computationally intensive parts of the application are performed in the host processor, the reconfigurable coprocessor plays a key role in taking charge of tasks that the host performs poorly, such as cycle-by-cycle data marshalling and ...

Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving increased attention. The design of such a hybrid reconfigurable processor involves a multitude of design decisions regarding the field-programmable structure as well as its system integration with the CPU core. Determining the impact of these design d...

Copyright © 2013 SciResPub. “FPGA IMPLEMENTATION OF HARDWARE TASK MANAGEMENT STRATEGIES” Assistant professor Sharan Kumar Electronics Department T.K.I.E.T Warananagar [email protected] Assistant professor Radhika R. Naik Electronics Department T.K.I.E.T Warananagar [email protected] Mr.Sagar.D.Bhopale Electronics Department T.K.I.E.T Warananagar [email protected] ABSTRA...

Embedded CPUs typically use much less power than desktop or server CPUs but provide limited or no support for floating-point arithmetic. Hybrid reconfigurable CPUs combine fixed and reconfigurable computing fabrics to balance better execution performance and power consumption. We show how a Stretch S6 hybrid reconfigurable CPU (S6) can be extended to natively support double precision floating-p...

Numerous research efforts in reconfigurable embedded processors have shown that augmenting a CPU core with a coarse-grained reconfigurable array for application-specific hardware acceleration can greatly increase performance and energy-efficiency. The traditional execution model for such reconfigurable co-processors however requires the accelerated function to fit onto the reconfigurable array ...

It was open for more than eight years to obtain an algorithm for computing the convex hull of a set of n sorted points in sub-logarithmic time on a reconfigurable mesh of size p n pn. Our main contribution is to provide the first breakthrough: we propose an almost optimal algorithm running in O((log logn)2) time on a reconfigurable mesh of size p n pn. With slight modifications this algorithm c...

The complexity of reconfigurable systems is in great part the complexity of the hardware-software environment where they are integrated. Many different reconfigurable architectures and respective development tools have been proposed in the literature, but few reconfigurable computing startups have succeeded at creating sustainable business models. The extraordinary infrastructure needed to oper...

Hartej Singh, Ming-Hau Lee, Guangming Lu, Fadi J. Kurdahi, Nader Bagherzadeh, University of California, Irvine, CA 92697 and Eliseu M. C. Filho, Federal University of Rio de Janeiro, Brazil Abstract: This paper introduces MorphoSys, a reconfigurable computing system developed to investigate the effectiveness of combining reconfigurable hardware with general-purpose processors for word-level, co...