The Garp project [3] quantitatively investigates the benefits of adding an on-chip dynamically reconfigurable coprocessor to a standard instruction processor. Intended for acceleration of loops, Garp’s coprocessor performs iteration control and both streaming and random memory accesses without assistance from the instruction processor. The companion project Garpcc [2] investigates whether new c...

xiii 1 Processor Design 1 1.1 Technology Trends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Application Trends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 Choice of Implementation Platforms . . . . . . . . . . . . . . . . . . . . . . 7 1.4 ASIP Design Methodologies . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5 Complexity Effective Desi...

The extensive use of reconfigurable computing devices has imposed a new category of processors, the dynamic instruction set processors (DISPs) that customize their instruction sets dynamically to the application needs. One of the major drawbacks of DISPs is the reconfiguration time needed to alter the instruction set, which is directly added to the program execution time discouraging the use of...

This paper describes the design and implementation of a 16 bit 4 stage pipelined Reduced Instruction Set Computer (RISC) processor on a Xilinx Spartan 3AN Field programmable gate array (FPGA). The processor implements the Harvard memory architecture, so the instruction and data memory spaces are both physically and logically separate. The RISC processor architecture presented in this paper is d...

The instruction sets of general-purpose microprocessors are designed to offer good performance across a wide range of programs. The size and complexity of the instruction sets, however, are limited by a need for generality and for streamlined implementation. The particular needs of one application are balanced against the needs of the full range of applications considered. For this reason, one ...

We present a framework for an efficient instruction-level machine simulator which can be used with existing software tools to develop and analyze programs for a proposed processor architecture. The simulator exploits similarities between the instruction sets of the emulated machine and the host machine to provide fast simulation. Furthermore, existing program development tools on the host machi...

We present a scalable, dynamically reconfigurable processor design that encompasses both reconfigurable circuitry and software-capable programmability for supercomputing applications on FPGAs. Advanced FPGA chips contain both reconfigurable logic blocks and embedded processor cores, providing the developer with an environment for embedded system design1. Since the reconfigurable fabric and the ...