In the process of compiling a computer programme, we consider the problem of allocating variables to registers within a loop. It can be formulated as a coloring problem in a circular arc graph (intersection graph of a family F of intervals on a circle). We consider the meeting graph of F introduced by Eisenbeis, Lelait and Marmol. Proceedings of the Fifth Workshop on Compilers for Parallel Comp...

ÐIn this paper, we examine the effectiveness of a new hardware mechanism, called Register Queues (RQs), which effectively decouples the architected register space from the physical registers. Using RQs, the compiler can allocate physical registers to store live values in the software pipelined loop while minimizing the pressure placed on architected registers. We show that decoupling the archit...

In testing certain systems, checking for burst errors is important. This is due to the fact that errors are confined to a certain number of bits. If signature analysis is used to test a circuit then the testing capabilities depend on the polynomial that defines the linear feedback shift register (LFSR) used in the test. In this paper we show that the LFSR that is suitable for checking for burst...

Register files account for a significant fraction of the power dissipation in modern RISC processors. Register file banking is an effective alternative to monolithic register files in embedded systems. We propose a profile-based technique to arrive at a customized energy-efficient bank configuration for a given application on a dual bank register file. The technique consists of a register renam...

Using the structure of Singer cycles in general linear groups, we prove that a conjecture of Zeng, Han and He (2007) holds in the affirmative in a special case, and outline a plausible approach to prove it in the general case. This conjecture is about the number of primitive σ-LFSRs of a given order over a finite field, and it generalizes a known formula for the number of primitive LFSRs, which...

This paper presents an architecture for programmable systolic arrays that provides simple and e cient systolic communication. The Brown Systolic Array is a linear implementation of this Systolic Shared Register architecture; a working 470-processor prototype system performs 108 MOPS. A 32-chip, 1504-processor implementation could provide 5 GOPS of systolic co-processing power on a single board.

In this paper, we study sequences generated by arbitrary feedback registers (not necessarily feedback shift registers) with arbitrary feedforward functions. We generalize the definition of linear complexity of a sequence to the notions of strong and weak linear complexity of feedback registers. A technique for finding upper bounds for the strong linear complexities of such registers is develope...

Distributed storage algorithms implement the abstraction of a shared register over distributed base objects. We study a specific class of storage algorithms, which we call amnesic: these have the pragmatic property that old values written in the implemented register might be eventually forgotten, i.e., they are not permanently kept in the storage and might be overwritten in the base objects by ...

This architecture features new mechanisms for the issuing and management of instructions in multi-cluster microarchitectures for superscalar microprocessors. Multi-cluster microarchitectures offer the potential for very substantial reductions in the energy expended per instruction executed, resulting in lower power microprocessors for many applications. Such gains are achieved by partitioning t...

This paper presents an architecture for programmable systolic arrays that provides simple and eecient systolic communication. The Brown Systolic Array is a linear implementation of this Systolic Shared Register architecture; a working 470-processor prototype system performs 108 MOPS. A 32-chip, 1504-processor implementation could provide 5 GOPS of systolic co-processing power on a single board.