Field-programmable logic (FPL) densities and performance have steadily improved, allowing DSP solutions to be integrated on a single FPL chip. The primary limitation of FPLs, in DSP-centric applications, is their intrinsically weak arithmetic performance compared to DSP microprocessors and ASICs. In some cases, distributed arithmetic (DA) has been used to mask FPL arithmetic inadequacies. The R...

Residue Number System (RNS) has computational advantages for large integer arithmetic. It provides the benefits of parallel, carry-free, and high-speed arithmetic in addition, subtraction, and multiplication. However, overflow detection, sign detection, magnitude detection, and division are time-consuming operations in RNS. The most interesting one of the above operations is division, and many ...

This whitepaper proposes the design and adoption of a new generation of Tensor Processing Unit (TPU) which has the performance of Google’s TPU, yet performs operations on wide precision data. The new generation TPU is made possible by implementing arithmetic circuits which compute using a new general purpose, fractional arithmetic based on the residue number system (RNS). www.digitalsystemresea...

In this paper, we present algorithmic and architectural transforms for low power realization of Residue Number System(RNS) based FIR lters. These transforms have been systematically derived so as to achieve power reduction by voltage scaling, switched capacitance reduction and reduction in signal activity. We show how some of the existing techniques can be suitably adopted to RNS based implemen...

Abstract: Modular adder is used in Residue Number System (RNS) addition. Moduli set with the form of 2-21(1≤ k≤ n-2) can offer excellent balance among the RNS channels for multi-channel RNS processing. In this paper, a Finite Impulse Response (FIR) filter using a novel algorithm and its Very Large Scale Integration (VLSI) implementation structure are proposed for modulo 2-2-1 adder. In the Modu...

Modular adder is one of the key components for the application of residue number system (RNS). Module set with the form can offer excellent balance among the RNS channels for multi-channels RNS processing. In this paper, a novel algorithm and its VLSI implementation structure are proposed for modulo2 n 2 k -1 adder. In the proposed algorithm, parallel prefix operation and carry correction techn...

Vector dot product or multiply accumulate (MAC) is a frequently used operation in digital signal processing algorithms. When implementing digital signal processors (DSPs) using field programmable gate arrays (FPGAs), significant area and speed advantages are possible if the implementation architecture has a direct mapping on the underlying structure of FPGAs. Such a synergy is present in both d...

Decoding in Residue Number System (RNS) based architectures can be a bottleneck. A high speed and flexible modulo decoder is an essential computational element to maintain the advantages of RNS. In this paper, a fast and flexible modulo decoder, based on the Chinese Remainder Theorem (CRT), is presented. I t decodes a set of residues into its equivalent representation in either unsigned magnitu...

It has been reported in the literature on computational neuroscience that a rat’s uncanny ability to dash back to a home position in the absence of any visual clues (or in total darkness, for that matter) may stem from its distinctive method of position representation. More specifically, it is hypothesized that the rat uses a multimodular method akin to residue number system (RNS), but with con...

Abstract The three-modulus residue number system (RNS) based on the moduli set {2, 2–1, 2–1} has been recently introduced. The modulo (2+1)-free feature of this set enables it to provide fast realization of modular addition and multiplication circuits of RNS arithmetic unit. But, the latest design of the RNS to binary (reverse) converter for the moduli set {2, 2–1, 2–1} relies on large hardware...