High speed and low power consumption are vital in ICs for high-speed optical communications systems. Some of the competing IC elements in this field include: Si-BJT (Silicon Bipolar Transistor), Si-CMOS (Silicon Field Effect Transistor), SiGe-BJT (Silicon Germanium Bipolar Transistor), GaAs-HBT (Gallium Arsenide Heterobipolar Transistor), GaAs-FET (Gallium Arsenide Field Effect Transistor), and...

The continuous scaling down of feature size in Silicon technology has resulted in several technological and fundamental hindrances. The researchers started to look for new nanoscale devices those can replace CMOS transistors in digital circuits. The nanowire transistor, FinFET, Carbon Nanotube field effect transistor (CNFET), tunnel field effect transistor (TFET), and single electron transistor...

In this article a low power and low latency 4-2 compressor has been presented. By using modified truth table and Pass Transistor Logic (PTL) a novel structure has been proposed which outperforms previous designs from the frequency of operation view point. The proposed design method has reduced the total transistor count considerably which will lead to reduced power consumption and smaller activ...

During the past few years, a lot of work has been done on behavioral models and simulation tools. But a need for modeling strategy still remains. The VHDL-AMS language supports the description of analog electronic circuits using Ordinary Differential Algebraic Equations (ODAEs), in addition to its support for describing discrete-event systems. For VHDL-AMS to be useful to the analog design ...

The effect of diameter variation on electrical characteristics of long-channel InAs nanowire metal-oxide-semiconductor field-effect transistors is experimentally investigated. For a range of nanowire diameters, in which significant band gap changes are observed due to size quantization, the Schottky barrier heights between source/drain metal contacts and the semiconducting nanowire channel are ...

Alloyed and compound contacts between metal and semiconductor transistor channels enable self-aligned gate processes which play a significant role in transistor scaling. At nanoscale dimensions and for nanowire channels, prior experiments focused on reactions along the channel length, but the early stage of reaction in their cross sections remains unknown. Here, we report on the dynamics of the...

This paper studies the effect of atomic layer deposition (ALD) temperature on the performance of top-down ZnO nanowire transistors. Electrical characteristics are presented for 10-μm ZnO nanowire field-effect transistors (FETs) and for deposition temperatures in the range 120°C to 210°C. Well-behaved transistor output characteristics are obtained for all deposition temperatures. It is shown tha...

Due to polarization of ions in crystals with noncentral symmetry, such as ZnO, GaN, and InN, a piezoelectric potential (piezopotential) is created in the crystal when stress is applied. Electronics fabricated using the inner-crystal piezopotential as a gate voltage to tune or control the charge transport behavior across a metal/semiconductor interface or a p-n junction are called piezotronics. ...