A power estimation approach is presented in which blocks of consecutive vectors are selected at random from a user-supplied realistic input vector set and the circuit is simulated for each block starting from an unknown state. This leads to two (upper and lower) bounds on the desired power value which can be quite tight (under 10% difference between the two in many cases). As a result, the powe...

 Abstract—This paper introduces m-inductiveness over a set of nodes S in sequential circuits. The m-inductive property can be used for equivalence-checking or improved sequential optimization. It allows the behavior of many next-state functions (not in S) to be changed while maintaining correctness at the primary outputs of a circuit. As such, it creates flexibility that can be used for sequen...

Assigning proper binary codes to the states of sequential circuits is a long studied problem known as state assignment. The choice of the numbers assigned to the states determines the final hardware structure and implementation requirements of the circuits. Conventional state assignment techniques can not be applied when arbitrary optimality criteria are defined. The problem can actually be see...

 This paper presents a BDD-based approach to perform logic partitioning for sequential circuits. We use a sequential machine to model a circuit and represent the machine by its transition relation. A heuristic algorithm based on the BDD representation of the transition relation is proposed to partition the sequential machine with minimum number of input/output pins. Using BDDs and their operat...

Realizing a sequential machine with shift registers is an attractive approach to the design for testability. It requires little extra circuit for scan and since feed-backs are always to the rst ip-op of a shift register test generation is expected to be easier than that for circuits with unstructured feedbacks. Though the shift register realization of sequential machines was studied by several ...

In this paper, a time and memory-efficient diagnostic fault simulator for sequential circuits is first presented. A distributed diagnostic fault simulator is then presented based on the sequential algorithm to improve the speed of the diagnostic process. In the sequential diagnostic fault simulator, the number of fault-pair output response comparisons has been minimized by using an indistinguis...

In general, sequential circuits are considered not to be random-testable. since a required lest sequence may grow exponentially with the number of f1ipflops. and it is very unlikely that a certain sequence occurs at random. This problem can be solved by combining tWO tasks: I) A small pan of the f1ipflops are made directly accessible, for instance by a partial scan path or by a built-in self-te...

Random pattern testing methods are known to result in poor fault coverage for most sequential circuits unless costly circuit modiication methods are employed. In this paper we propose a novel approach to improve the random pattern testability of sequential circuits. We introduce the concept of holding signals at primary inputs and scan ip-ops for a certain length of time instead of applying a n...

Alloy uses a first-order relational logic for modeling designs. The Alloy Analyzer translates Alloy formulas for a given scope, i.e., a bound on the universe of discourse, to Boolean formulas in conjunctive normal form (CNF), and subsequently checks them using propositional satisfiability solvers. We present SERA, a novel algorithm that compiles a relational logic formula for a given scope to a...

This paper proposes a detailed design analysis of sequential circuits for quantum-dot cellular automata (QCA). This analysis encompasses flip-flop (FF) devices as well as circuits. Initially, a novel RS-type FF amenable to a QCA implementation is proposed. This FF extends a previous threshold-based configuration to QCA by taking into account the timing issues associated with the adiabatic switc...