Metal–oxide–semiconductor field-effect transistors ~MOSFETs! with a wire-channel and wrap-around-gate ~WW! structure were fabricated using electron beam lithography and reactive ion etching. The smallest devices have a 35 nm channel width, a 50 nm channel thickness, and a 70 nm channel length. Measurements showed that as the channel width of WW MOSFETs decreased from 75 to 35 nm short channel e...

As the continuous down scaling of MOSFET device is required to increase the speed and packaging density of it, but it reduces the device characteristics in terms of short channel effect and reverse leakage current. At present, the single gate MOSFET reaching its scaling limit. These limitations associated with scaling give birth to number of innovative techniques which includes the use of diffe...

Currents evoked in neurons of the vertebrate CNS by the glutamate agonist N-methyl-D-aspartate (NMDA) exhibit a marked voltage dependence in the presence of extracellular Mg. At the single-channel level, the addition of external Mg alters single-channel openings from long-lived events to many very short events grouped into bursts of openings. These bursts apparently result from short interrupti...

High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper r...

This paper has studied drain induced barrier lowering(DIBL) for Double Gate MOSFET(DGMOSFET) using analytical potential model. Two dimensional analytical potential model has been presented for symmetrical DGMOSFETs with process parameters. DIBL is very important short channel effects(SCEs) for nano structures since drain voltage has influenced on source potential distribution due to reduction o...

The one-dimensional, cylindrical nature of single-walled carbon nanotubes SWCNTs suggests that the ideal gating geometry for nanotube field-effect transistors FETs is a surround gate SG . Using vertical SWCNTs templated in porous anodic alumina, SGs are formed using top-down processes for the dielectric/metal depositions and definition of the channel length. Surround gates allow aggressive scal...