Keywords: Single event effect Fault tolerance Triple and double modular redundancy Latchup protection switch ASIC design a b s t r a c t The paper presents CMOS ASICs which can tolerate the single event upsets (SEUs), the single event transients (SET), and the single event latchup (SEL). Triple and double modular redundant (TMR and DMR) circuits in combination with SEL protection switches (SPS)...

Error containment is an important concept in fault-tolerant system design, and techniques like voting are applied to mask erroneous outputs, thus preventing their propagation. In this presentation we will use the example of DARTS, a fault-tolerant distributed clock generation scheme in hardware, to demonstrate that metastability is a substantial threat to error containment. We will illustrate h...

We present a new method to estimate Single Event Upsets (SEU) in a hadron accelerator environment, which is characterized by a complicated radiation spectrum. Our method is based on first principles, i.e. an explicit generation and transport of nuclear fragments and detailed accounting for energy loss by ionization. However, instead of simulating also the behaviour of the circuit, we use a Weib...

Transcription repression plays important roles in preventing crucial regulatory proteins from being expressed in inappropriate temporal or spatial domains. LEUNIG (LUG) and SEUSS (SEU) normally act to prevent ectopic expression of the floral homeotic gene AGAMOUS in flowers. LUG encodes a protein with sequence similarities to the yeast Tup1 corepressor. SEU encodes a plant-specific regulatory p...

Memory blocks are the most significant features of any design, frothy of its silicon area, functionality and dependency. SRAM memories are the main benefactors to the Soft Error Rate of the system. Since error detecting and correcting codes are commonly available and especially effective against most types of Single Event Effects, Multiple Bit Upsets and advanced errors gathering may conquer th...

Ground level upsets have been observed in computer systems containing large amounts of random access memory (RAM). Atmospheric neutrons are most likely the major cause of the upsets based on measured data using the Weapons Neutron Research (WNR) neutron beam.