نتایج جستجو برای: symbolic designs and signs
تعداد نتایج: 16840129 فیلتر نتایج به سال:
We describe a methodology for verifying system-on-chip designs. In our methodology, the problem of verifying system-on-chip designs is decomposed into three tasks. First, we verify, once and for all, the standard bus interconnecting IP Cores in the system . The next task is to verify the glue logic, which connects the IP Cores to the buses. Finally, using the verified bus protocols and the IP c...
welding is one of the key components of numerous manufacturing industries, which has potential physical and chemical health hazards. many components of welding fumes can potentially affect the lung function. this study investigates the effects of welding fumes on lung function and respiratory symptoms among welders of an automobile manufacturing plant in iran. this historical cohort study asses...
Kabud masque belongs to Abul al – Mozaffar Shah Jahan from Turkaman Agh Quyunloo tribe. The build­ing was finished in 870 AH by Jan Beyg Khatoon (Ja­han shah’s wife). There are various plant and geomet­ric features and inscriptions in the masque. The masque inscriptions are mostly created by two Kufi and Tholth writing and are related to the surrounding illustrations and...
This paper describes the use of a symbolic modeling tool and a methodology we developed for modeling processes in business re-engmeering projects. DECmodel, a symbolic modeling tool, was used to build dynamically activated, working scale models of processes. Models were developed for business, systems, and organizational processes at several levels of detail, and integraled into a large dynamic...
This paper presents a new testing atmtegy for networks ofinteracting FSMa. The approach allows w to genemte test patterns for faults in the network by separately handling the network’s components. The proposed algorithms are j%ly symbolic; therefore, they allow the manipulation of large designs. Experimental results, though preliminary, are promising.
An approach for interpreted sequential veriication at diier-ent levels of abstraction by symbolic simulation is proposed. The equivalence checker has been used in previous work to compare two designs at rt-level. We describe in this paper the automatic veriication of gate-level results of a commercial synthesis tool against a behavioral speciication at rt-level. The symbolic simulator has to co...
This research examines a chronic problem in academic settings – inappropriate copying or misuse of source materials–i.e., plagiarism. We conduct a computer-based writing experiment to examine the effects of psychological and situational characteristics on subjects’ propensity to misappropriate text. Specifically, we examine to what extent such misappropriations may be explained by available tec...
Using 3.3 pb of data collected with the CMD-2 detector in the 720 – 840 MeV c.m. energy range, the branching fraction of the conversion decay ω → πee has been measured: B(ω → πee) = (8.19 ± 0.71± 0.62) · 10. The upper limits for the branching fractions of the following conversion decays have been obtained at the 90% confidence level: B(ρ → πee) < 1.6 · 10, B(ρ → ηee) < 0.7 · 10 and B(ω → ηee) <...
The increasing popularity of System-on-Chip (SoC) circuits results in many new design challenges. One major challenge is to ensure the functional correctness of such complicated circuits. While most existing verification techniques work well at the Register Transfer (RT) and gate levels, the growing trend is to extend verification to higher-level design abstractions in order to catch bugs early...
Intention is to show how the concepts of Peircean semeiotic can be transformed to interactivist ones, and what restrictions this transformation brings along to the application of Peircean concepts especially to biosemiotics. The basic interactive re-interpretation of Peircean semeiotic for biosemiotics can be done with three levels of representation. At the first level, the concept of minimal (...
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