We introduce ternary wavelets, based on an interpolating 4-point C ternary stationary subdivision scheme, for compressing fractal-like signals. These wavelets are tightly squeezed and therefore they are more suitable for compressing fractal-like signals. The error in compressing fractal-like signals by ternary wavelets is at most half of that given by four-point wavelets (Wei and Chen, 2002). H...

An MOS ternary-logic family is proposed, which is comprised of a set of inverters, NOR gates, and NAND gates. These gates are used to design basic ternary arithmetic and memory circuits. The circuits thus obtained are then used to synthesize complex ternary arithmetic circuits and shift registers. The ternary circuits developed are shown to have some significant advantages relative to other kno...

In high speed applications, multipliers and their associated circuits like accumulators, half adders, and full adders consume a significant portion. Therefore, it is necessary to increase their performance as well as size efficiency. In order to reduce the hardware complexity which ultimately reduces an area and power, energy efficient full adders plays crucial role in Wallace tree multiplier. ...

In this paper, our main focus is to reduce computation delay proposed in previous FFA algorithm based FIR digital filter. Parallel FIR filter structure with fast finite-impulse response (FIR) along with symmetric coefficients reduces the hardware cost, under the condition that the number of taps is a multiple of 2 or 3. . The proposed parallel FIR structures exploit the inherent nature of symme...

In this manuscript, an unusual adaptive FIR filter using distributed arithmetic (DA) for area efficient design is implemented. DA is bit-serial computational action and uses parallel look-up table (LUTs) apprise and equivalent implementation of filtering and weight-update operations to appliance high throughput filter rates irrespective of the filter length. The full adder based conditional sig...

In this paper, an optical half adder is designed using photonic crystals. One of the features its small size. design structure, it has been tried to have a size, shorter delay and high contrast ratio so that can be used in integrated circuits. For sum carry outputs, obtained 15.4 dB 7.4 dB, respectively. addition, proposed structure size 70 µm2. The use simple point defects, caused maximum time...