Testing of high-speed integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a BIST methodology such that high performance devices can be tested on relatively low performance testers. In addition, also a full BIST technique is add...

A Built-In Self-Test (BIST) approach is presented for system-level testing of the programmable Input/Output (I/O) buffers in Field Programmable Gate Arrays (FPGAs) and configurable System-on-Chip (SoC). We discuss implementation methods for the BIST approach, including parameterized VHDL and FPGA-specific hardware design description languages. The fault detection capabilities and limitations of...

Built-In Self-Test (BIST), as the name suggests is a technique in which the circuit is capable of testing itself. This paper presents two techniques: Linear Feedback Shift Register (LFSR) and Cellular Automata (CA), used for test pattern generation and test response analysis in a typical BIST circuit. Both LFSR and CA are analyzed based on their construction and characteristics. A comparison of...

This paper presents a segment weighted random built-in self test (SWR-BIST) technique for low power testing. This technique divides the scan chain into segments of different weights. Heavily weighted segments have more biased probability than lightly weighted segments. Heavily weighted segments are placed closer to the end of scan chain than the lightly weighted segments so the scan-in transiti...

The design of an asynchronous block sorter and issues relating to its testability are discussed in this paper. The sorter takes an input data stream and sends it to the output sorted in descending order. The testable structure of the block sorter is implemented using the built-in self test (BIST) design methodology. A novel technique for changing the operation mode of the sorting cells of the b...

The topic of this thesis is related to testing of very large scale integration circuits. The thesis presents the idea of optimizing mixed-mode built-in self-test (BIST) scheme. Mixed-mode BIST consists of two phases. The first phase is pseudo-random testing or partial pseudo-exhaustive testing (P-PET). For the faults not detected by the first phase, deterministic test patterns are generated and...

In this paper an effective Built-In Self-Test (BIST) scheme for the shifter-accumulator pair (accumulation performed either by an adder or an ALU) which appears very often in embedded processor, microprocessor or DSP datapaths is introduced. The BIST scheme provides very high fault coverage (>99%) with respect to the stuck-at fault model for any datapath width with a regular, very small and cou...

We present the first delay-fault testing approach for Field Programmable Gate Arrays (FPGAs), applicable for on-line testing as well as for off-line manufacturing and system-level testing. Our approach is based on Built-In Self-Test (BIST), it is comprehensive, and does not require expensive external test equipment (ATE). We have successfully implemented this BIST approach for delay-fault testi...

We present an enhanced built-in self-test (BIST) architecture for high-performance circuits. Test patterns are generated by reseeding a twisted-ring counter. We show that a small number of seeds is adequate for generating test sequences that embed complete test sets for the ISCAS benchmark circuits. The seed patterns can either be stored on-chip or scanned in using a low-cost, slower tester. Th...

Introduction In the virtual component (VC) integration business, the embedded DRAM is a key VC to realize high bit density and high bandwidth performance, thus the low-cost testing of DRAM-integrated LSI is an emerged problem. The DRAM test usually includes a fail-bit (address) search to repair the memory cell defects with redundancy, requiring long time for wafer probing. A DRAM BIST drastical...