Due to increasing system complexity and growing competition and costs, powerful techniques are needed to design and analyze manufacturing systems. One of the most popular techniques to do performance analysis is simulation. However, simulation-based analysis cannot guarantee the correctness of a system. Our research focuses on examining other methods to make performance analysis and functional ...

In this paper, we report on an application of the validation and veri cation tool kit Uppaal in the design and analysis of a prototype gear controller, carried out in a joint project between industry and academia. The gear controller is a component in the control system operating in a modern vehicle, implementing the gear change algorithm. We give a detailed description of the formal model of t...

In this bachelor’s thesis an approach for Flow Systems in UPPAAL is introduced. This approach is then used to implement a model for an industry use-case: the pre-production machine Lithography Wafer Scanner System by company A. It is during this implementation concluded that this model is not valid. Next, a tool is written to generate Gantt charts from traces of arbitrary timed UPPAAL models. T...

The paper presents a novel algorithm for computing worst case execution time (WCET) or maximum termination time of real-time systems using the timed automata (TA) model checking technology. The algorithm can work on any arbitrary diagonal-free TA and can handle more cases than previously existing algorithms for WCET computation, as it can handle cycles in TA and decide whether they lead to an i...

System level models are abstractions of hardware systems which should make it easier to apply capacity limited formal verification tools to validate them. However, due to the sequential nature of languages such as SystemC [1], extensive use of co-routine style threading for expressing concurrency, and oft-used mixed abstraction styles, make it hard to create abstractions suitable for formal ver...

In this paper, we show how to apply recent tools for the automatic synthesis of robust and near-optimal controllers for a real industrial case study. We show how to use three different classes of models and their supporting existing tools, UPPAAL-TIGA for synthesis, PHAVER for verification, and SIMULINK for simulation, in a complementary way. We believe that this case study shows that our tools...

Özet Biçimsel do§rulama bir sistemin do§rulanmas n n tasar m a3amas nda yap lmas na izin veren ve son y llarda kullan m h zla artan bir yöntemdir. Bu bildiride almaç planlay c bile3eni tasar m n n gerçek zaman gereksinimleri dahil edilerek biçimsel do§rulanmas sunulmaktad r. Bu kapsamda say sal almaç planlay c bile3eninin biçimsel modelinin ve gereksinimlerinin UPPAAL model denetim arac ile bel...

We report on a case study in which the model checker Uppaal is used to formally model parts of Zeroconf, a protocol for dynamic configuration of IPv4 link-local addresses that has been defined in RFC 3927 of the IETF. Our goal has been to construct a model that (a) is easy to understand by engineers, (b) comes as close as possible to the informal text (for each transition in the model there sho...

We describe a prototype extension of the Uppaal real-time model checking tool with symmetry reduction. The symmetric data type scalarset, which is also used in the Murφ model checker, was added to Uppaal’s system description language to support the easy static detection of symmetries. Our prototype tool uses state swaps, described and proven sound earlier by Hendriks, to reduce the space and me...