نتایج جستجو برای: verification rules generation
تعداد نتایج: 543340 فیلتر نتایج به سال:
We have a large database consisting of sales transactions. We investigate the problem of online mining of association rules in this large database. We show how to preprocess the data e ectively in order to make it suitable for repeated online queries. The preprocessing algorithm takes into account the storage space available. We store the preprocessed data in such a way that online processing m...
This paper presents a scheme for the dynamic generation of context rules which are useful for modifying the behaviour of mobile devices according to the social and physical settings of their users. Existing context-aware systems employ a pool of predefined rules which will be executed whenever a context of interest is sensed and captured. Defining rules at design time, however, has the followin...
This paper and a companion paper [32] together define, present and apply a methodology for integration of formal verification by automata-based model-checking into a commercially supported object-oriented software development process. This paper defines and illustrates a set of design rules for OOA models with executable semantics, which lead to automata models with tractable state spaces. The ...
Software is used in many safetyand security-critical systems. Software development is, however, an error-prone task where a software developer tries to precisely formalize in a programming language their imprecise ideas about a program. Formal methods help to reduce this problem. These methods add another layer to the software development allowing to formalize and to check desired properties of...
In this study, we developed a method for converting SysML state machine diagrams into Promela models that can be verified using the SPIN model checking tool. The Promela code generated in our approach is a sequential verification model that simplifies the verification process when used in the early stages, and also prevents state explosion in the verification process. Thus, using the sequential...
This paper focuses on usefulness of a plant model for model-checking of untimed properties of logic controllers. Verification results obtained on a case study by using the symbolic model-checker NuSMV and three methods: verification of the only controller, constraints-based verification, in which the plant is simply modeled as a set of physical constraints, and model-based verification, that re...
80 0740-7475/04/$20.00 © 2004 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers TO COMPETE IN THE MARKETPLACE, all semiconductor products have tight time-to-market requirements. With design complexity exploding, functional verification is now on the critical path to RTL signoff and relies mainly on extensive vector simulation. A typical microprocessor requires bi...
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