This paper describes the initial development of a translator from VHDL-AMS code into HSPICE, as a contribution to the group of CAD-EDA tools in the field of analog design. Analog synthesis tools are not as developed as digital ones but the arise of VHDLAMS, a superset of VHDL, can help to their development. In this work, we present some features of a translator capable to synthesise analog circ...

To perform cosimulation, an interface design of VHDL simulation is needed. This interface is responsible for communicating packets between any VHDL simulator and the cosimulation backplane, PeaCE, which is a Ptolemy extension as codesign environment. The interface also manages the simulation for correct timed cosimulation. By the automatic interface generation mechanism, the interface is genera...

This paper gives operational semantics for a subset of VHDL in terms of abstract machines. Restrictions to the VHDL source code are the niteness of data types, and the absence of quantitative timing infor-mations. The abstract machine of a design unit is built by composition of the abstract machines for its embedded processes and blocks. The kernel process in our model is distributed among the ...

We present an application tool dedicated to superconducting circuits design. Based on the use of VHDL-AMS language on System Vision software, we developed an innovating approach with top-down methodology to specify the RSFQ circuits. We take the example of a sigma-delta bandpass ADC and show the different processes used to design it. The demonstration shows the complete system in mixed signal l...

Electrical Engineering (ABSTRACT) Hardware description languages (HDLs) such as VHDL have made it possible for circuit and board designs to be done without resorting to paper, allowing computers to manage the design database and automate the translation between various representations of the system. Although VHDL modeling can provide a bonanza of benefits, VHDL models must be used effectively t...

Simulations and prototyping have been a very important part of the electronics industry since a very long time. In recent years, FPGA‘s have become increasingly important and have found their way into all kind of digital system design This paper presents a novel, easy and efficient approach of implementation and verification of VHDL code using Simulink and then to regenerate the optimized VHDL ...

The study of fat body receptors (e.g., VHDL receptor) in Lepidoptera has been irksome due to the fact that isolation and purification of these proteins are difficult and resulted in extremely low yields. A rapid and efficient method is presented for the purification of Helicoverpa zea VHDL receptor by the use of VHDL-biotin ligand complexed to streptavidin coated magnetic beads. The technique c...

This paper discusses the use of fault models for the diagnosis of hardware designs written in the VHDL hardware description language. VHDL designs are concurrent programs consisting of hundreds of thousands of lines of source code, whose testing and debugging is a very time-consuming process. Building on an abstract representation that allows the search for errors in even the largest VHDL progr...

This paper describes the use of model-based diagnosis for locating bugs in hardware designs. We restrict our view to hardware designs written in a subset of the commonly used hardware description language VHDL. This subset includes all synthesizeable (register transfer level) programs. This are programs which can be automatically converted into a gate level description without changing their be...