Fixed-point hardware implementations of signal processing algorithms can often achieve higher performance with lower computational requirements than a floating-point implementation. However, the design of such systems is hard due to the difficulty of addressing the quantization issues. This paper presents an optimization approach to determining the wordlengths of fixed-point operators in a spee...

We consider the behaviour of digital control systems from the point of view of modeling intersample behavior , and the eeects of quantizations and nite wordlength computations. Our purpose in this paper is to investigate the dependence of these two eeects on the sampling rate. We show that there is essentialy a tradeoo between guarding against these two eeects, in that fast sampling will genera...

Coppersmith, Krawczyk, and Mansour ([CKM93]) presented at Crypto '93 a promising stream cipher, the shrinking generator. It is based on linear shift registers with linear feedback. The output bits of one shift register decide which of the output bits of the other shift registers are used and which are discarded. The design is well suited for hardware implementation. In software shift registers ...

This paper presents an integer discrete cosine transform (IntDCT) with only dyadic values such as k/2n (k, n ∈ N). Although some conventional IntDCTs have been proposed, they are not suitable for lossless-to-lossy image coding in low-bit-word-length (coefficients) due to the degradation of the frequency decomposition performance in the system. First, the proposed M-channel lossless Walsh-Hadama...

In this contribution the impact of finite signal wordlengths on the performance of digital systems for arbitrary sampling rate conversion (ASRC), where input and output sampling rates are derived from independent clock generators, is investigated. For two different approaches to ASRC the noise power due to both, input/output quantisation and multiplication roundoff errors, is determined as a fu...

The objective of the AMDREL (Architectures and Methodologies for Dynamic Reconfigurable Logic) project is to develop methodologies, tools and intellectual property blocks to be integrated in a partly dynamically reconfigurable System-on-Chip (SoC) implementation platform for the efficient realization of wireless communications systems. The proposed tools, reusable intellectual property blocks a...

This paper presents a reconfigurable FFT architecture for variable length and multistreaming WiMax wireless standard. The architecture processes 1 stream of 2048-pt FFT, up to 2 streams of 1024-pt FFT or up to 4 streams of 512-pt FFT. The architecture consists of 11 SDF pipelined stages and radix-2 butterfly is calculated in each stage. The sampling frequency of the system is varied in accordan...

| In this paper a method for parameterizing orthogonal wavelet transforms is presented. The parameter space is given by the rotation angles of the orthogonal 22{ rotations used in the lattice lters realizing the stages of the wavelet transform. Diierent properties of orthogonal wave-let transforms can be expressed in this parameter space. Then, the parameter space is restricted to the set of ro...

ASIC or FPGA implementation of a finite wordlength PID controller requires a double expertise: in control system and hardware design. In this paper, we only focus on the hardware side of the problem. We show how to design configurable fixed-point PIDs to satisfy applications requiring minimal power consumption, or high control-rate, or both together. As multiply operation is the engine of PID, ...

This paper describes an efficient algorithm for the design of multiplierless approximately linear-phase lattice wave digital (LWD) filters (parallel connections of two all-pass filters). The coefficient optimization is performed in two basic steps. First, a nonlinear optimization algorithm is used for determining a parameter space of the infinite-precision coefficients including the feasible sp...