Digital system such as system-on-chip microprocessor generally requires Phased-Locked Loop (PLL) for clock generation. However, traditional analog PLL typically contains several important components not included in a standard cell library, such as resistor and low leakage capacitor, which makes it difficult to integrate into a digital system. In addition, its performance is limited by process, ...

A fast-lock and portable all-digital delay-locked loop (ADDLL) with 90◦ phase shift and tunable digitally-controlled phase shifter (DCPS) for DDR controller applications are presented. The ADDLL can achieve small phase-shift error in 1.3◦ at 400MHz and locking time of less than 13 clock cycles, making it very suitable for low-power DDR controller with power-down mode. The proposed DCPS provides...

Phase Locked Loops (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal.A phase locked loop can track input frequency or it can generate a frequency that is the multiple of input frequency .PLLs are widely employed in radio,tele communications,computers etc.In order to overcome the disadvantage of analog PLLs such as the effect of leak...

This paper presents a new quantization noise suppression method for a time-to-digital converter (TDC) and proposes an all-digital phase-locked loop (ADPLL) architecture using only standard cell logic gates. Using a new multiple input multiple output (MIMO) quantization noise suppression method provides an order of √ 2N improvement in TDC resolution with N parallel TDC channels. Suppressed noise...

Abstract This paper presents the complete design of a phase locked loop-based clock synthesizer for reconfigurable analog-to-digital converters. The was implemented in TSMC 65 nm CMOS process technology and presented results were obtained from extracted layout view with parasitics. generates frequencies ranging 40 to 230 MHz considering reference frequency 10 supply voltage 1.2 V. Worst case cu...

This survey is devoted to the dynamic analysis of the Costas loop. In particular the acquisition process is analyzed in great detail. Acquision is most conventiently described by a number of frequency and time parameters such as lock-in range, lock-in time, pull-in range, pull-in time, and hold-in range. While for the classical PLL equations for all these parameters have been derived (many of t...