This paper considers the problem of partitioning analog integrated circuits for hierarchical symbolic analysis based on determinant decision diagrams (DDDs). The objective is to use DDDs with the minimum number of vertices to represent all the symbolic expressions. We show that the problem can be formulated as that of multi-level multi-way hyper graph partitioning with balance constraints, and ...

A generalized parameter-level statistical MOS model, called SMOS, capable of generating statistically significant model decks from intraand inter-die parameters statistics is described. Calculated model decks preserve the inherent correlations between model parameters while accounting for the dependence of parameter variance on device separation distance and device area. Using a Monte Carlo app...

The use of Pareto-optimal performance fronts in emerging design methodologies for analog integrated circuits is a keystone to overcome the limitations of traditional design methodologies. However, most techniques to generate the fronts reported so far neglect the effect that the surrounding circuitry (such as the load impedance) has on the Pareto-front, thereby making it only realistic for the ...

Analog fault diagnosis is a field of paramount importance, and test signal generation is an important prerequisite for analog fault detection. Several stimuli have been used as input test vectors. This study presents a novel approach for the adoption of classical methods and signals for fault detection. This involves the use of asymmetrical periodic signals and comparison of their effectivity i...

A major concern in mixed-signal circuits is the noise injected by the digital circuits into sensitive analog circuits. Of particular interest in this work is the problem with large capacitive coupling between the digital clock network and the substrate shared with the analog circuits. It is in general more easy to reduce low frequency noise compared with high frequency noise. Therefore, we have...

This paper investigates a hybrid evolutionary-based design system for automated sizing of analog integrated circuits (ICs). A new algorithm, called competitive co-evolutionary differential evolution (CODE), is proposed to design analog ICs with practical user-defined specifications. On the basis of the combination of HSPICE and MATLAB, the system links circuit performances, evaluated through el...

Pedagogy This paper presents some of the techniques used at the University of Massachusetts Dartmouth to introduce analog microelectronic system design to undergraduate electrical engineering students. The following paper discusses a wide range of assignments that attempt to address student’s varied learning styles. These assignments not only take the form of traditional homework, but also incl...

The test of Analogue and Mixed-Signal (AMS) cores requires the use of expensive AMS testers and accessibility to internal analogue nodes. The test cost can be considerably reduced by the use of Built-In-Self-Test (BIST) techniques. One of these techniques consists in generating analogue test signals from digital test patterns (obtained via Σ∆ modulation) and converting the responses of the anal...

Digital circuit design is extensively assisted bymodern automation tool unlike analog design which is still a manual task because of the complexity of the interactions between devices. This paper presents a semi-automated analog placement based on margin tolerances controlled by the designer by creating analog circuits organized in row similar to digital circuits structure. The results show the...

The idea is using advanced analog design methodology for LVLP to push the basic analog circuit design toward LVLP applications. It is necessary to point out that this report is just an outline of what the final project will accomplish. Those parameters mentioned above are subjected to be changed during the design process to achieve higher performance or more realistic. Parameter Name Value Para...