The design and VLSI implementation of a new ASIC which performs the operation of grey-scale dilation using both image and structuring element threshold decomposition is presented in this paper. The minimum rate of external operations of this ASIC is 30 MPix/sec and it can handle 3 x 3 pixel images and structuring elements of up to 4-bit resolution. The high speed of operation is achieved using ...

A Field-programmable Gate Array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configurati...

Hardware implementation quality will be considered as an important factor for evaluating the NIST SHA-3 competition candidates in the second round. The most traditional and popular hardware im­ plementation method is designing ASICs with standard cells. However, to benchmark 14 second round SHA-3 ASIC designs based on a fair and comprehensive methodology can be very challenging because of the u...

Today's interactive 3D-applications on Pes demand efficient hardware support for functionality, e.g. shading and texture mapping. In this paper, I present an ASIC that integrates most of the 3D-reIated functionality defined in Intel's de-facto standard 3DR. As the chip was designed for real time environmental simulation systems, the main focus has been on texture mapping, which provides the mos...

This document describes the hardware and the software of a Front-End Electronics Test Station developed to test and characterize the Front-End ASIC for the LHCb Muon chambers. This ASIC, an 8-channel amplifier, shaper and discriminator with baseline restoration, processes read-out signals generated by Multi-Wire Proportional and GEM chambers located in a high radiation environment. It is almost...

This paper describes a semi-hierarchical approach applied to the layout of a challenging multiprocessor ASIC. The ASIC contains several hundred single bit processors on a single chip in a 130 nm technology. The chip is targeted at the massive parallel processing of simple tasks that occur in huge quantities, for example, during hardware emulation. The paper focuses on the complex interconnect n...

VLSI circuits design allows today to consider new modes of implementation for electrical controls. However, design techniques require an adaptation effort that few designers, too accustomed to the software approach, provide. The authors of this article propose to develop a methodology to guide the electrical designers towards optimal performances of control algorithms implementation. Thus, they...

Extracellular acidification has been shown to generate action potentials (APs) in several types of neurons. In this study, we investigated the role of acid-sensing ion channels (ASICs) in acid-induced AP generation in brain neurons. ASICs are neuronal Na(+) channels that belong to the epithelial Na(+) channel/degenerin family and are transiently activated by a rapid drop in extracellular pH. We...

This thesis describes the SD-34 system verification ASIC that will provide a cost efficient solution in calibrating/verifying ATE systems when testing high-speed memory devices. The heart of the ASIC is a High Resolution Skew Detector (HRSD) which converts in-phase as well as out-of-phase skew into a usable signal for use off-chip using a novel time-to-voltage conversion (TVC) technique. Multip...

Molecular and behavioral evidence suggests that acid-sensing ion channels (ASICs) contribute to pain processing, but an understanding of their precise role remains elusive. Existing ASIC knock-out mouse experiments are complicated by the heteromultimerization of ASIC subunits. Therefore, we have generated transgenic mice that express a dominant-negative form of the ASIC3 subunit that inactivate...