Conventional hardware description languages do not provide all the facilities required for efficient behavioural modelling of asynchronous systems. This paper presents a new HDL incorporating CSP-like channel communication and other features making it more suitable for this task. A model of a simple microprocessor is used to illustrate how the language and tools can be applied to real design pr...

When designing asynchronous systems, the problems of hazards becomes an important issue. This paper deals with the hazard-free implementation of asynchronous logic in a look-up table based FPGA. First, the definitions of hazards and techniques to deal with them in gate-level asynchronous circuits are surveyed. Then the look-up table (LUT) model and its associated timing properties are presented...

Most asynchronous processor Instruction Set Architectures (ISA) are based on a single type of underlying asynchronous circuit design style. Asynchronous processor ISAs are entirely dependent on the type of asynchronous design style chosen and can support a limited set of simple applications only. Design reuse is typically difficult to realize in such cases. In this paper, we show a behavioral m...

The paper is concerned with the modeling of the electrical signals and of the asynchronous circuits by } 1 , 0 { → R functions and asynchronous automata. The equations of the asynchronous automata are written and solved; the stability, the fundamental mode of operation, the semi-modularity and some aspects of semantics of the propositional temporal logic as seen from behind asynchronous automat...

Eventual failure detectors, such as Ω or ♦P, can make arbitrarily many mistakes before they start providing correct information. This paper shows that any detector implementable in a purely asynchronous system can be implemented as a function of only the order of most-recently heard-from processes. The finiteness of this representation means that eventual failure detectors can be enumerated and...

As universities expand so too does the diversity of students. Widening participation requires higher education providers to be responsive to the needs of all students by ensuring an accessible and engaging learning environment. Today’s cohort includes an increased number of students with autism, a spectrum condition that has the potential to be either beneficial or detrimental to their success ...

An innovative online approach to executive development is described. The approach utilizes asynchronous and synchronous elements, required submission of assignments, and other features resembling those of online college courses. Design of the learning experience, though, has been observant of the various motivations of busy executives. The approach so far has resulted in high rates of course co...

The lack of proven mechanisms for transferring data between multiple synchronous islands has been a major impediment for applying globally asynchronous locally synchronous (GALS) techniques to SoC design. We have implemented on a VLSI test chip three alternative solutions to fill the gap: an arbitrated bus, a switch, and a self-timed ring. Circuit details and various extensions of the basic rin...

A testing scenario in the sense of De Nicola and Hennessy is developed to measure the worst-case eeciency of asynchronous systems using dense time. For all three variants considered, it is shown that one can equivalently use discrete time; in the discrete versions, one variant coincides with an approach based on discrete time in Vog95b], and thus we can clarify the assumptions behind this appro...

In this paper, we present FASE (Faster Asynchronous Systems Evaluation), a tool for evaluating the worst-case efficiency of asynchronous systems. The tool is based on some well-established results in the setting of a timed process algebra (PAFAS: a Process Algebra for Faster Asynchronous Systems). To show the applicability of FASE to concrete meaningful examples, we consider three implementatio...