Delay testing of designs that contain intellectual property (IP) cores is challenging. We propose a method that can test paths traversing both IP cores and user-defined blocks. It employs a highly efficient BDD-based path modeling method and an associated ATPG technique. Experimental results show that it can robustly test selected paths without using extra logic, and protects the intellectual p...

− There’re mainly two different situations for testing PLD (Programmable Logic Device) devices. One is testing of blank chips that haven’t been programmed; the other is testing of ASIC (Application Specific Integrated Circuit) devices that have been programmed. This paper presents a test method for programmed ASIC devices, including auto test and ATPG (Auto Test Pattern Generation) method for b...

A method to perform diagnostic test generation in sequential circuits by modifying a conventional test generator is presented. The method utilizes circuit netlist modification along with a forced value at a primary input in the modified circuit. Techniques to reduce the computational effort for diagnostic test pattern generation in sequential circuits are also presented. Speed-up of the diagnos...

A new method of test-per-clock BIST design for combinational circuits is proposed. The fundamental problem of matching the PRPG outputs with the required test patterns is solved as a general design problem in the field of combinational logic. A test set generated by an ATPG is compared with the PRPG generated sequence. The solution is based on a novel search algorithm, which identifies the best...

The increasing design complexity and shrinking feature size of hardware designs have created resource intensive design verification and manufacturing test phases in the product life-cycle of a digital system. On the contrary, time-to-market constraints require faster verification and test phases; otherwise it may result in a buggy design or a defective product. This trend in the semiconductor i...

In this paper, a new approach for generating test vectors that detects faults in combinational circuits is introduced. The approach is based on automatically designing a circuit which implements the -algorithm, an automatic test pattern generation (ATPG) algorithm, specialized for the combinational circuit. Our approach exploits fine-grain parallelism by performing the following in three clock ...

Design validation is essential to ensuring low cost design of reliable systems, and solutions for validation problems are coming from the manufacturing test community. The purpose of this panel is to summarize the current state of design validation research, and to outline important directions for future research in the area. The panel will include people from both industry and academia to give...

The ASIC design flow is rapidly moving towards higher description levels, and most design activities are now performed at the RT-level. However, test-related activities are lacking behind this trend, mainly since effective fault models and test pattern generation tools are still missing. This paper proposes techniques for implementing a high-level ATPG. The proposed algorithm mixes a code cover...

As technology scales down, digital VLSI circuits are prone to many manufacturing defects. These defects may result in functional and delay-related circuit failures. The number of test escapes grows when is downscaled. Small delay (SDDs) hidden (HDDs) critical importance industries today since they the source most reliability problems. Improving quality creating new methods, algorithms, designs ...