Avoiding delay jitter is essential to achieve high throughput for TCP. In particular, delay spikes can cause spurious timeouts. Such timeouts force TCP into slow-start, which may reduce congestion window sizes drastically. Consequently, there may not always be data available for transmission on bottleneck links. For HS-DSCH, jitter can occur due to varying interference. Also, properties of the ...

Most commercial multicomputers use space-slicing schemes in which each scheduling decision has an unknown impact on the future: should a job be scheduled, risking that it will block other larger jobs later, or should the processors be left idle for now in anticipation of future arrivals? This dilemma is solved by using gang scheduling, because then the impact of each decision is limited to its ...

The Input-Buffered Wavelength-Routed (IBWR) switch is a promising switching architecture for slotted Optical Packet Switching (OPS) networks. The benefits of the IBWR fabric are a better scalability and lower hardware cost, when compared to output buffered OPS proposals. A previous work characterized the scheduling problem of this architecture as a type of matching problem in bipartite graphs. ...

Multiple-instruction-issue processors seek to improve performance over scalar RISC processors by providing multiple pipelined functional units in order to fetch, decode and execute several instructions per cycle. The process of identifying instructions which can be executed in parallel and distributing them between the available functional units is referred to as instruction scheduling. This pa...

Packet scheduler plays the central role in determining the overall performance of the 3GPP long-term evolution (LTE) based on packet-switching operation. In this paper, a novel minimum transmit power-based (MP) packet-scheduling algorithm is proposed that can achieve power-efficient transmission to the UEs while providing both system throughput gain and fairness improvement. The proposed algori...

Execution speed of programs on modern computer architectures is sensitive, by a factor of two or more, to the order in which instructions are presented to the processor. To realize potential execution efficiency, it is now customary for an optimizing compiler to employ a heuristic algorithm for instruction scheduling. These algorithms are painstakingly hand-crafted, which is expenseive and time...

Large-grain synchronous data ow graphs or multi-rate graphs have the distinct feature that the nodes of the data ow graph re at di erent rates. Such multi-rate large-grain data ow graphs have been widely regarded as a powerful programming model for DSP applications. In this paper we propose a method to minimize bu er storage requirement in constructing rate-optimal compile-time (MBRO) schedules...

In the multi-core and multiprocessor domain there are two scheduling approaches, global and partitioned scheduling. Under global scheduling each task can execute on any processor while under partitioned scheduling tasks are allocated to processors and migration of tasks among processors is not allowed. Under global scheduling the higher utilization bound can be achieved, but in practice the ove...

This paper presents the design, implementation and experimental evaluation of a practical region-based partial dead code elimination (PDE) algorithm on predicated code in the ORC compiler framework. Existing PDE algorithms are not applicable on predicated code due to the existence of if-converted branches in the program. The proposed algorithm processes all PDE candidates in a worklist and reas...

This paper deals with a permutation flow-shop scheduling problem with finite intermediate storage (PFSFIS) between successive machines so as to minimize makespan. In such a problem the intermediate storage capacity constraints are considered besides the machine-related constraints usually discussed in the general permutation flow-shop. This feature adds extra difficulties to the scheduling prob...