A new precision full-wave rectifier employing only two differential difference current conveyors, which is very suitable for CMOS technology implementation, is presented. The proposed rectifier is the voltage-mode circuit, which offers high-input and low-output impedance hence it can be directly connected to load without using any buffer circuits. PSPICE is used to verify the circuit performanc...

the voltammetric behaviour of sulfadoxine (sdn) was studied at a glassy carbon electrode in 0.2 m phosphate buffer solutions using cyclic, differential-pulse (dpv) and square wave voltammetry (swv). the dependence of the current on ph, concentration, and scan rate was investigated to optimize the experimental conditions for the determination of sdn. the oxidation process was shown to be diffusi...

This paper describes the circuit design of a programmable logic array chip using four-phase dynamic circuits, operating at a nominal cycle time of 230 nanoseconds. Bootstrap circuit techniques are used to obtain high function and performance by satisfying some special requirements of PLA designs. These include a simple means for two-bit partitioning of the data inputs, a noninverting buffer cir...

The continuing scaling down of complementary metal oxide semiconductor (CMOS) has led researchers to build new devices with nano dimensions, whose behavior will be interpreted based on quantum mechanics. Singleelectron devices (SEDs) are promising candidates for future VLSI applications, due to their ultra small dimensions and lower power consumption. In most SED based digital logic designs, a ...

Decoder design involves choosing the optimal circuit style and figuring out their sizing, including adding buffers if necessary. The problem of sizing a simple chain of logic gates has an elegant analytical solution, though there have been no corresponding analytical results until now which include the resistive effects of the interconnect. Using simple RC models, we analyze the problem of opti...

With the progress of VLSI technology, delay buffer plays an important role affecting the circuit design and performance. This paper presents the design of low power buffer using clock gating and gated driver tree. Since delay buffers are accessed sequentially, it adopts a gated clock ring counter addressing scheme. The ring counter employs double edge triggered (DET) flip flops instead of tradi...

Planar superstrate CuInS2 (CIS) solar cell devices are fabricated using totally solution-processed deposition methods. A titanium dioxide blocking layer and an In2S3 buffer layer are deposited by the spray pyrolysis method. A CIS2 absorber layer is deposited by the spin coating method using CIS ink prepared by a 1-butylamine solvent-based solution at room temperature. To obtain optimum annealin...

This paper presents a temperature measurement system without the input buffer. A voltage follower or a buffer is required to minimize the influence of the ADC input impedance in the thermistor temperature measurement system. In such system, a high performance operational amplifier is usually required to prevent the noise and distortion due to the additional circuit. Negative power is also neces...

Integrated quantum optical circuits are now seen as one of the most promising approaches with which to realize single-photon quantum information processing. Many of the core elements for such circuits have been realized, including sources, gates and detectors. However, a significant missing function necessary for photonic quantum information processing on-chip is a buffer, where single photons ...

TLP retry mechanism is an effective measure of PCI Express to ensure data reliable transmissions. The paper theoretically analyzes reasons for retransmission, operating rules of retransmission and factors affecting the size of retry buffer. On this basis, proposes a circuit structure of implementing TLP retry mechanisms, describing the implementation process of retry management, and conducts fu...