In this paper a yield model for single chip VLSI processors with two level on-chip caches is derived. Using this model and trace tiven simulations the distribution of the faulty cache blocks into the first and second level caches can be determined so as to achieve a significant yield enhancement with the min imum performance degradation.

This paper presents the MANTRA I machine, an SIMD neuro-computer based on a square systolic array of dedicated processing elements (PEs). A VLSI custom chip, called GENES IV containing 2 2 PEs is at the heart of the system. This machine implements suucient instruction and data ows to keep the array's utilization rate close to 100 %.

The Katz-Sarnak Density Conjecture states that zeros of families L-functions are well-modeled by eigenvalues random matrix ensembles. For suitably restricted test functions, this correspondence yields upper bounds for the families' order vanishing at central point. We generalize results on nth centered moment distribution to arbitrary functions. On computational side, we use our improved formul...