A high-speed triple-modulus frequency divider (FD) is designed and fabricated in a 90-nm CMOS process. With three pairs of nMOS switches inserted in the signal paths of the regenerative divider, the FD can offer three selectable division ratios of 1/2, 1/3, and 1/4. The corresponding behavior model of the proposed divider is utilized to explain the operation principle and analyze the locking ra...

In this paper, dual-frequency O-shaped 3-way Bagley power divider is designed and analysed. Equal split power division is achieved at arbitrary design Frequencies. In this structure, two-section transmission line transformer is used to realize the dual-frequency operation. This paper describes a new Bagley power divider on a single-layer micro strip line that can reduce the occupied area. To va...

Abstract—This paper presents a novel tri-band unequal Wilkinson power divider. The proposed structure is derived from the conventional unequal Wilkinson power divider by replacing the quarter-wavelength branch lines and quarter-wavelength transformers with the extended T-shaped short stubs and three-section transformers respectively. The first and third operating frequencies of the proposed Wil...

This work describes the design of a divder technique Low-power techniques are applied in the design of the unit, and energy-delay tradeoffs considered. The energy dissipation in the divider can be reduced by up to 70% with respect to a standard implementation not optimized for energy, without penalizing the latency. In this dividing technique we compare the radix-8 divider is compared with one ...

This letter presents an inductor-loaded 2:1 regenerative frequency divider operating up to 331.2 GHz in an InP HBT process, which, to the best of authors’ knowledge, is the fastest frequency divider reported thus far. On-wafer measurement shows that the divider is operating from 304.8 GHz to 331.2 GHz, with output power from 27 dBm to 12.3 dBm (no probe loss correction), while dissipating 85.5 ...

Abstract: A method for calibrating multi-decade inductive voltage dividers has been developed which makes it possible to determine both the inphase and the quadrature error for ratios of i /11, i = 1, 2, ..., 10 in the frequency range from 400 Hz to 5 kHz. Calibration is made by comparing the divider under test against a reference two-stage divider having a ratio winding with 11 identical secti...

A new broadband in-phase power divider based on multilayer technology is presented. A simple design procedure is developed for the proposed multilayer power divider. An S-band four-way multilayer power divider was designed and measured. The simulated results are compared with the measured data, and good agreement is reported. The measured 15 dB return loss bandwidth is demonstrated to be about ...

Abstract—A compact dual-band power divider for GSM/DCS applications is proposed in this letter. Novel planar artificial transmission lines are applied to miniaturize the power divider and achieve wideband response. The proposed dual-band power divider is about 37% of conventional one. The design principle, simulated and measured results are all discussed. The measured results show that good per...

The implementation of a programmable high speed divider for a CMOS Frequency Synthesizer, using 0.35 μm CMOS technology, is described. The Frequency Synthesizer is part of a RF transceiver to work in the 2.4 GHz ISM (Industrial, Scientific and Medicine) band. The programmable divider employs: a divide-by-32/33 dual-modulus prescaler composed by a divide-by-4/5 synchronous counter, using the Ext...

The objective of this project is to develop a Programmable Frequency divider design for multi GHz PLL System implementation on FPGA using VHDL (hardware description language). The frequency divider architecture features 6 parallel divider chains, each one of them implementing a single division ratio. The desired frequency division ratio is then selected using the four control bits of an output ...