This work describes a 10-bit 40MS/s pipelined analog-to-digital converter (ADC) which is used in IEEE 802.11a WLAN system. This pipelined ADC is consisted of one sample-and-hold (S/H) circuit and nine uniform pipelined stages. In this pipelined ADC, the resolution for the S/H circuit and each single pipelined stage is up to 12 bit and 14 bit respectively at 8 MHz input frequency. The spurious f...

The design of a 500 MHz oscillator in a 65 nm CMOS process using a 2 GHz bulk acoustic wave (BAW) resonator is presented. A digital frequency control is implemented using a switched capacitor bank in parallel to the resonator. The tuning range is up to 500 kHz with a minimum step of 200 Hz. The oscillator core uses a differential topology and is designed for low phase noise (2128 dBc/Hz at 100 ...

This paper proposes an ultra compact LC-VCO. Due to the speed-up of CMOS digital circuits, jitter of ring oscillators is becoming a critical problem. Even though a LCVCO has a better phase noise, a layout size of on-chip inductor is a problem as a clock generator. Thus, the proposed LC-VCO consists of a very compact stacked-spiral inductor and active components placed beneath the inductor. The ...

This paper deals with a method for low cost power electronic substratescreation, which are used for power electronic devices. Direct bond copper (DBC) technology is suitable for creating substrates with excellent thermal and electrical conductivity and good mechanical properties. Furthermore, DBC allows to create copper layers with the thickness of hundreds micrometers in one processing step. I...

—A low-phase-noise, low-power Ka-band VoltageControlled Oscillator (VCO) using cross-coupled pair configuration is presented. The Ka-band VCO circuit uses 0.18 μm SiGe BiCMOS technology. The VCO has low phase noise of -114.6 dBc/Hz at 1 MHz offset from 32.12 GHz carrier frequency and can be tuned from 30.17 to 33.48 GHz. The figure of merit is -202.1 dBc/Hz. The power consumption of the VCO wi...

Based on a physical understanding of phase-noise mechanisms, a passive LC filter is found to lower the phase-noise factor in a differential oscillator to its fundamental minimum. Three fully integrated LC voltage-controlled oscillators (VCOs) serve as a proof of concept. Two 1.1-GHz VCOs achieve 153 dBc/Hz at 3 MHz offset, biased at 3.7 mA from 2.5 V. A 2.1-GHz VCO achieves 148 dBc/Hz at 15 MHz...

In this paper we introduce an ultra low power CMOS LC oscillator and analyze a method to design a low power low phase noise complementary CMOS LC oscillator. A 1.8GHz oscillator is designed based on this analysis. The circuit has power supply equal to 1.1 V and dissipates 0.17 mW power. The oscillator is also optimized for low phase noise behavior. The oscillator phase noise is -126.2 dBc/Hz an...

This paper proposes an ultra compact LC-VCO. Due to the speed-up of CMOS digital circuits, jitter of ring oscillators is becoming a critical problem. Even though an LC-VCO has a better phase noise, a layout size of on-chip inductor is a problem as a clock generator. Thus, the proposed LC-VCO consists of a very compact stacked-spiral inductor and active components placed are beneath the inductor...

An energy efficient ultra-wideband (UWB) transmitter based on the novel transmitted reference pulse cluster (TRPC) modulation scheme is presented. The TRPC-UWB transmitter integrates, namely, wideband active baluns, wideband I-Q modulator based up-conversion mixer, and differential to single-ended converter. The integrated circuits of TRPC-UWB front end is designed and implemented in the 130-nm...