We present the results of an InP HBT device development process. We have developed a new HBT device fabrication approach that represents a major departure from traditional compound semiconductor manufacturing techniques. The new generation of deep submicron InP-based HBTs presented here uses an ion implanted subcollector and offers significantly improved performance, integration, and device rel...

Silicon microcombs developed at our laboratory for the precision alignment and assembly of large-area foil optics have previously been demonstrated to achieve submicron-level assembly repeatability with submillimeter-thick flat substrates. In this article we report on a double-side deep reactive-ion etch fabrication process using silicon-on-insulator wafers which was developed to improve the mi...

We present in this paper an overview of circuit techniques dedicated to design reliable low-voltage (1-V and below) analog functions in deep submicron standard CMOS processes. The challenges of designing such low-voltage and reliable analog building blocks are addressed both at circuit and physical layout levels. State-ofthe-art circuit topologies and techniques (input level shifting, bulk and ...

We consider multi-processor systems on chips (MPSoCs) that will be designed and produced in deep submicron technologies (DSM) with minimal features in the [100− 25]nm range. Such systems will be designed using preexisting components, such as processors, controllers and memory arrays. The major design challenge will be to provide a functionally-correct, reliable operation of the interacting comp...

The layout design to improve uniform ESD current distribution in multi-finger MOSFET devices for better ESD robustness is investigated in a 0.18-μm salicided CMOS process. The multi-finger MOSFET, without adding the pick-up guard ring inserted into its source region, or with the vertical direction of power line connection, can sustain a higher ESD level. The layout of I/O cell can be drawn more...

As CMOS technology scales to deep-submicron dimensions, designers face new challenges in determining the proper balance between aggressive high-performance transistors and lower-performance transistors to optimize system power and performance for a given application. Determining this balance is crucial for battery-powered handheld devices in which transistor leakage and active power limit the a...

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This paper describes the ideas and philosophy behind a new compact model (CM) for deep-submicron MOSFETs, called Xsim, which has been developed from scratch over the past few years. Similarities to and differences from existing popular models are pointed out. The opinions on many controversial debates in the CM field are given. The ultimate goal of the CM development in the context of technolog...