Adders are one of the widely used digital components in digital integrated circuit design. The Carry Select Adder (CSA) provides a good compromise between cost and performance in carry propagation adder design. However, conventional CSA is still area-consuming due to the dual ripple carry adder (RCA) structure. In this paper, modification is done at gate-level to reduce area and power consumpti...

This paper presents a new early output hybrid input encoded asynchronous full adder designed using dual-rail and 1-of-4 delay-insensitive data codes. The proposed full adder when cascaded to form a ripple carry adder (RCA) necessitates the use of a small relative-timing assumption with respect to the internal carries, which is independent of the RCA size. The forward latency of the proposed hyb...

In this paper, we present the design and experimental evaluation of complementary energy path adiabatic logic (CEPAL) based 1 bit full adder circuit. A simulative investigation on the proposed full adder has been done using VIRTUOSO SPECTRE simulator of cadence in 0.18μm UMC technology and its performance has been compared with the conventional CMOS full adder circuit. The CEPAL based full adde...

A Multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, Digital Signal Processors (DSPs), Microprocessors etc., A Wallace tree multiplier is an improved version of tree based multiplier architecture. It uses 4:2, 5:2 compressors and a Carry Select Adder (CSA) to reduce the latency and power consumption. In conventional methods, 10T XNOR s...

Among the emerging technologies recently proposed as alternatives to the classic CMOS, Quantum-dot cellular automata (QCA) is one of the most promising solutions to design area efficient and very high speed digital circuits. As transistors decrease in size more and more of them can be accommodated in a single die, thus increasing chip computational capabilities. However, transistors cannot get ...

The terahertz optical asymmetric demultiplexer (TOAD) or semiconductor amplifier (SOA)-assisted Sagnac switches have been used to construct an all-optical 4-bit carry skip adder. This design aims satisfy the high speed and accuracy requirements of modern ultrafast digital transmission. Using a combination multiplexer full adder, we describe When compared ripple adder look-ahead may be employed ...

This paper presents FPGA-based design of hybrid adder with the optimal bit-width configuration(out of alarge number of possible configurations) of each of the sub-adders constitute the proposed hybrid adder using a high level automated methodology. Algebraicoptimization model for the hybrid adderis built to produce the best choice of types and bitwidths of the sub-adders. In context of this wor...

In this paper a novel architecture of multiplier and accumulator (MAC) for high speed arithmetic is presented. The architecture adopts radix-4 modified booth algorithm (MBA) and hybrid carry save adder, in which the accumulator that has the largest delay in MAC was merged into Carry save adder (CSA) block. The performance of final adder block, which determines critical path of the architecture,...

Single-Electron-Technology (SET) is one of the future technologies distinguished by its small and low power devices. SET also provides simple and elegant solutions for threshold logic gates (TLG’s). This paper presents the design of an optimal TLG adder implemented in SET. It provides a detailed procedure for designing capacitive– input SET TLG’s for building the adder. The paper also presents ...