The paper presents a Design Space Exploration (DSE) experiment which has been carried out in order to determine the optimum FPGA–based Variable-Length Decoder (VLD) computing resource and its associated instructions, with respect to an entropy decoding task which is to be executed on the FPGA-augmented TriMedia/CPU64 processor. We first outline the extension of the TriMedia/CPU64 architecture, ...

In this paper we present a flexible performance estimation tool calledNessie developed toprovide system-on-chip designerswith automated multi-objective design space exploration and its related tool called Yeti building and executing reusable closed-formed models. After reviewing the existing closed-formed expressions based and application/platform mapping performance estimation tools, we propos...

Recent approaches on language-driven Design Space Exploration (DSE) use Architectural Description Languages (ADL) to capture the processor architecture, generate automatically a software toolkit (including compiler, simulator, and assembler) for that processor, and provide feedback to the designer on the quality of the architecture. It is important to verify the ADL description of the processor...

We describe V–SAT, a tool for performing design space exploration of System-On-Chip (SOC) architectures. The key components of V–SAT include EXPRESSION, a language for specification of the architecture, SIMPRESS, a simulator generator for analysis/evaluation of the architecture, and the V– SAT GUI front-end for easy specification and detailed analysis. We give a brief overview of the components...

Early energy estimation is increasingly important in MultiProcessor System-On-Chip (MPSoC) design. Applying traditional approaches, which consist in delaying the estimation until the architectural layout has been produced, is inefficient and prevents the rapid exploration of alternative architectures. In this paper, we present a framework for architectural exploration as part of MPSoC design. O...

Single-chip parallel computer architectures may provide a solution to the wire latency problem expected as device fecture sizes shrink. Hence the development of efficient single-chip parallel computer is an active area of research. Extensive design space exploration of such architectures requires an architectural simulator that evaluates both power and performance. The available parallel comput...

For many years, research on FPGA-type programmable hardware architectures has focused mainly on optimising regular non-hierarchical architectures. In the exploration of their design space, some design parameters have a significant impact on the layout area, which is directly related to interconnect delay. An estimation of this impact can be derived from a prediction of the area of the basic FPG...

Designing custom solutions has been central to meeting a range of stringent and specialized needs of embedded computing, along such dimensions as physical size, power consumption, and performance that includes real-time behavior. For this trend to continue, we must find ways to overcome the twin hurdles of rising non-recurring engineering (NRE) costs and decreasing time-to-market windows by pro...

Exploring the design space of computer architectures generally consists of a trial-and-error procedure where several architectural configurations are evaluated by using simulation techniques. The final goal of the multiobjective design space exploration (DSE) process is the identification of architectural configurations optimal for a set of target objective functions, typically power consumptio...

This paper addresses the problem of component selection, task assignment and task scheduling for distributed embedded computer systems. Such systems have a large number of constraints of different nature, such as cost, execution time, memory capacity and limitations on resource usage. Previous approaches have concentrated on a specific class of requirements and thus they limit number of constra...