A new physical and continuous BSIM (Berkeley Short-Channel IGFET Model) I–V model in BSIM3v3 is presented for circuit simulation. Including the major physical effects in state-of-the art MOS devices, the model describes current characteristics from subthreshold to strong inversion as well as from the linear to the saturation operating regions with a single I–V expression, and guarantees the con...

We investigate the performances of 18 nm gate length AlInN/GaN, InP/InGaAs heterostructure and a Silicon double gate MOSFET, using 2D Sentaurus TCAD simulation. The heterostructure device uses lattice-matched wideband Al0.83In0.17N /InP and narrowband GaN / In0.53Ga0.47As layers, along with high-k Al2O3 as the gate dielectric, while silicon based device uses SiO2 gate dielectric. The device has...

In this paper, an 18nm dopingless asymmetrical junctionless (AJ) double gate (DG) MOSFET has been designed for suppressed short channel effects (SCEs) low power applications. A desired ON and OFF state current ratio with subthreshold performance parameters under limit, is the major focus of proposed transistor. Different sensitivity AJ DG such as drain extension, length overlapping oxide thickn...

A multi-nanosheet field-effect transistor (mNS-FET) device was developed to maximize gate controllability while making the channel in form of a sheet. The mNS-FET has superior for stacked channels; consequently, it can significantly reduce short-channel effect (SCE); however, punch-through inevitably occurs bottom portion that is not surrounded by gates, resulting large leakage current. Moreove...

The metal oxide semiconductor field effect transistor is the building block of VLSI(Very Large Scale Industry).Minimum featrure size of the ICs has shurnk consideably over the time of several decades. This results in a chip with the same functionality in a smaller area, or chips with more functionality in the same area.As a consequence,the number of transistor has increased over time. When gate...

Influence of dielectric materials as gate oxide on various short channel device parameters using a 2-D device simulator has been studied in this paper. It is found that the use of high-k dielectrics directly on the silicon wafer would degrade the performance. This degradation is mainly due to the fringing field effect developed from gate to source/drain. This fringing field will further generat...

Article history: Received 2 February 2016 Received in revised form 10 May 2016 Accepted 16 May 2016 Available online 9 June 2016 Thiswork proposes a numerical charge-based newmodel to describe the drain current for triple gate junctionless nanowire transistors (3G JNT). The drain current is obtained through a numerical integration of a single expression that physically describes the junctionles...

We developed a double-recess etching process and a new Digital-Oxide-Deposition (DOD) technique to fabricate 180nm low-threshold GaN Metal-OxideSemiconductor Double Heterostructure Field Effect Transistors (MOS-DHFET). Two device layer structures, InGaN channel design and InGaN back-barrier design, were employed to improve the confinement of TwoDimensional Electron Gas (2DEG) and mitigate the s...

In this paper, a fin-shaped field effect transistor (FinFET) structure which uses ground plane concept is proposed and theoretically investigated. The ground plane reduces the coupling of electric field between the source and drain reducing drain-induced barrier lowering (DIBL). To assess the performance of the proposed structure, some device characteristics of the structure have been compared ...

We present an analytical and continuous dc model for undoped cylindrical surrounding double-gate (CSDG) MOSFETs for which the drain current and subthreshold model is written as an explicit function of the applied voltages for the wireless telecommunication systems to operate at the microwave frequency regime of the spectrum. The model is based on a unified charge control model developed for thi...