We have demonstrated high-performance deep-submicron inversion-mode InGaAs MOSFETs with gate lengths down to 150 nm with record Gm exceeding 1.1 mS/μm. Oxide thickness scaling is performed to improve the on-state/off-state performance and Gm is further improved to 1.3 mS/μm. HBr pre-cleaning, retro-grade structure and halo-implantation processes are first time introduced into III-V MOSFETs to s...

Over the past 50 years of the semiconductor industry, the size of MOSFETs has been scaled down obeying the Moore’s law: feature sizes of transistors are scaled at a rate of approximately 0.7 times every 18 months. However, as CMOS technology approaches nanoscale region, researchers face with critical technology barrier known as short channel effect. While the gate voltage fully controls the cha...

In the light of a modified two-dimensional Poisson equation, an analytical model for the threshold voltage Vth of deep-submicrometre MOSFETs is developed, which can show Vth’s nonlinear dependence on drain voltage Vds . Meanwhile, by introducing a normalized effective gate voltage Vgtx to obtain continuous channel charge characteristics from the subthreshold to the strong inversion region and p...

In this paper, we compare four SRAM circuits. They are the conventional SRAM1, the SRAM2 with power switches on VSS line, the SRAM3 with switches on VDD line, and the SRAM4 with switches on both VDD and VSS lines, respectively. Among the four SRAMs, the SRAM2 shows the smallest amount of leakage, because its subthreshold leakage is most suppressed by its BODY and Drain-Induced Barrier Lowering ...

This paper presents a closed-form compact model for the undoped double-gate (DG) MOSFET under symmetrical operation. This charge-based model aims at giving a comprehensive understanding of the device from the circuit design point of view. Both static and dynamic models are derived in terms of simple analytic relationships based on our new explicit formulation of the mobile charge density. Our a...

An InAlAs/InGaAs HEMT with an InAs-rich barrier spacer (In0.52Al0.48As) to reduce the parasitic resistance is reported. Devices were obtained with a source resistance of 170 V-mm. A 40 nm gate length In0.7Ga0.3As HEMT with Lside 1⁄4 100 nm and tins 1⁄4 10 nm shows excellent transconductance and subthreshold characteristics including gm 1⁄4 1.6 mS/mm, DIBL 1⁄4 122 mV/V and S 1⁄4 80 mV/ dec at VD...

Scaling of metal-oxide-semiconductor transistors to smaller dimensions has been a key driving force in the IC industry. This work analysis the gate leakage current behavior of nano scale MOSFET based on TCAD simulation. The Sentaurus Simulator simulates the high-k gate stack structure of N-MOSFET for analysis purpose. The impact of interfacial oxide thickness on the gate tunneling current has b...