This work presents an 11 GS/s 1.1 GHz bandwidth interleaved ∆Σ DAC in 65 nm CMOS for the 60-GHz radio baseband. The high sample rate is achieved by using a two-channel interleaved MASH 1-1 architecture with a 4-bit output resulting in a predominantly digital DAC with only fifteen analog current cells. Two-channel interleaving allows the use of a single clock for the logic and the multiplexing w...

This paper studies encoding/decoding function of artificial spiking neurons. First, we investigate basic characteristics of spiketrains of the neurons and fix parameter value that can minimize variation of spike-train length for initial value. Second we consider analog-to-digital encoding based upon spike-interval modulation that is suitable for simple and stable signal detection. Third we pres...

A number of state-of-the-art low power consuming digital delta-sigma modulator (∆Σ) architectures for digital-to-analog converters (DAC) are presented in this thesis. In an oversampling ∆Σ DAC, the primary job of the modulator is to reduce the word length of the digital control signal to the DAC and spectrally shape the resulting quantization noise. Among the ∆Σ topologies, error-feedback modul...

A general analysis on stochastic timing errors (clock or timing jitter) is presented for Digital to Analog Converters (DAC). The obtained results describe the effects of (non)correlated errors for given signal properties, and reveal the nature of the tradeoff between oversampling ratio, resolution and noise shaping in the context of noise-shaped DACs and Continuous-Time (CT) Sigma Delta (EA) AD...

An 8-bit coarse digital-to-analog converter (DAC), which adopts both array and tree-type decoders, is combined with a 2-bit fine interpolation DAC to reduce RC time delay and die area of a column driver for LCD-HDTV applications. Error amplifiers drive a pair of column lines in the output buffer to realize rail-torail voltage swing with a high slew rate. The design has been fabricated in 0.3 μm...

This paper presents an 8-GS/s, 12-bit input ∆Σ DAC with 200-MHz bandwidth in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ∆Σ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. The two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each ch...

This paper presents a reconfigurable sigma-delta audio Digital-to-Analog Converter (DAC) which is suitable for embedded FPGA applications. The Sigma-Delta Modulator (SDM) design can be configured as a 3rd or 5th order SDM and allows different input word lengths. Different input sampling rates are also entertained by employing a programmable interpolator. The DAC accepts 16-/18-/20-/24-bit PCM d...