0-7803-7542-4/02 $17.00 © 2002 IEEE Panel P7.4 ITC INTERNATIONAL TEST CONFERENCE SELECTIVE OPTIMIZATION OF TEST FOR EMBEDDED FLASH MEMORY Roger Barth Intel Corporation The Problem Embedded memory has never been the easiest memory to test since it is generally hidden behind a large amount of intervening circuitry. Over the years, DAT (Direct Access Test) has eased the problem for the test engin...

MEMORIES CONTINUE TO be a key technology driver in the semiconductor industry. Advanced memory technologies are the trendsetters for integration levels and chip density. Over the past two decades, we have witnessed the on-chip integration of large cache memories as computer architects and chip designers have grappled with the challenges of high power consumption and the need to reduce memory ac...

Embedded systems have become ubiquitous and as a result optimization of the design and performance of programs that run on these systems have continued to remain as significant challenges to the computer systems research community. This dissertation addresses several key problems in the optimization of programs for embedded systems which include digital signal processors as the core processor. ...

The power of dynamic memory management can be used to produce more flexible control applications without compromising the robustness of the applications. It is demonstrated how automatic memory management, or garbage collection (GC), can be used in a system that has to comply with hard real-time demands while still preserving the predictability of the system. A suitable garbage collection algor...

The current approach to developing mixed-criticality systems is by partitioning the hardware resources (processors, memory and I/O devices) among the different applications. Partitions are isolated from each other both in the temporal and the spatial domain, so that low-criticality applications cannot compromise other applications with a higher level of criticality in case of misbehaviour. New ...

As the capacity of eld programmable gate arrays (FPGAs) increases, on-chip memories have become an essential component to provide high degree of on-chip integration. Modern FPGAs, such as Actel MX 27] and DX FPGAs 26], Altera FLEX10K, FLEX10KE 29] and APEX20K device family 30], and Vantis VF1 series FPGAs 28], provide embedded memory blocks (EMBs) to be used as on-chip memories. Compared with t...

As the size of FPGA devices grows following Moore’s law, it becomes possible to put a complete manycore system onto a single FPGA chip. The centralized memory hierarchy on typical embedded systems in which both data and instructions are stored in the off-chip global memory will introduce the bus contention problem as the number of processing cores increases. In this work, we present our explora...

Shape memory alloy (SMA) wires can be embedded in a host material to alter the stiffness or modal response and provide vibration control. The interaction between the embedded SMA and the host material is critical to applications requiring transfer of loads or strain from the wire to the host. Although there has been a significant amount of research dedicated to characterizing and modeling the r...

We propose a methodology to improve the performance of embedded processors running data-intensive applications by allowing embedded software to manage on-chip memory on an application-specific or task-specific basis. We provide this management ability with a novel hardware mechanism, column caching. Column caching provides software with the ability to dynamically partition the cache. Data can b...

This paper proposes a high-level formalism, called Abstract Functional and Timing Graph (AFTG), for describing a memory architecture, which combines logical functionality and timing. After translation of the AFTG into the form a timed automaton, we are able to compute the response times of the modeled memory, and check their consistency with the values specified in the datasheet. We also addres...