Most of the signal processing algorithms using floating point arithmetic, which requires millions of operations per second to be performed. For such stringent requirement design of fast, precise and efficient circuit is needed. This article present an IEEE 754 floating point unit using carry look ahead adder and radix-4 modified Booth encoder multiplier algorithm and the design is compared in t...

This brief presents a fast sign detection algorithm for the residue number system moduli set {2 n+1 − 1, 2 n − 1, 2 n }. First, a sign detection algorithm for the restricted moduli set is described. The new algorithm allows for parallel implementation and consists exclusively of modulo 2n additions. Then, a sign detection unit for the moduli set {2 n+1 − 1, 2 n − 1, 2 n } is proposed based on t...

New VLSI circuit architectures for addition and multiplication modulo 2 1 and 2 1 are proposed that allow the implementation of highly efficient combinational and pipelined circuits for modular arithmetic. It is shown that the parallel-prefix adder architecture is well suited to realize fast end-around-carry adders used for modulo addition. Existing modulo multiplier architectures are improved ...

A design methodology for implementing fast, easily testable arithmetic-logic units (ALU’s) is presented. Here, we describe a set of fast adder designs, which are testable with a test set that has either ( ) complexity (Lin-testable) or (1) complexity (C-testable), where is the input operand size of the ALU. The various levels of testability are achieved by exploiting some inherent properties of...

A design methodology for implementing fast, easily testable arithmetic-logic units (ALU’s) is presented. Here, we describe a set of fast adder designs, which are testable with a test set that has either ( ) complexity (Lin-testable) or (1) complexity (C-testable), where is the input operand size of the ALU. The various levels of testability are achieved by exploiting some inherent properties of...

This paper presents a performance analysis of hybrid 1-bit full-adder circuit design. The adder cell is dissected into smaller modules. The modules are analyzed and calculated extensively. To explore good-drivability, noise-robustness, and low-energy operations for deep sub micrometer to explore hybrid-CMOS style design. Hybrid-CMOS design style uses various CMOS logic style circuits to constru...

In this paper, the various low power delay product full adder circuits have been analyzed. The adder is the fundamental blocks of any arithmetic circuit, so even a small reduction power or delay leads to improved performance of the circuit with optimal power saving. A 10T adder technique is the famous low power delay product full adder circuits with minimum transistor count. A new 10T technique...

We present a self-contained and detailed description of the parallel-prefix adder of Ladner and Fischer. Very little background is assumed in digital hardware design. The goal is to understand the rational behind the design of this adder and view the parallel-prefix adder as an outcome of a general method. This essay is from the book: Shimon Even Festschrift, edited by Goldreich, Rosenberg, and...

In this paper, a proposed 1-bit hybrid full adder design employing both transmission gate logic and complementary metal– oxide–semiconductor (CMOS) logic is reported. The design is implemented for 1-bit Ripple Carry Adder and then is extended for 64-bit Ripple Carry Adder. The circuit is implemented using Mentor Graphics tools 130nm technology. The performance parameters such as delay, area, to...

We consider an original ternary number system called the ternary mirror-symmetrical number system in the article. It is a synthesis of the classical ternary symmetrical number system and the number system with an irrational base called Bergman’s number system. The main engineering result is a development of an original matrix and pipeline ternary mirror-symmetrical adder, which can be used for ...