A high-speed triple-modulus frequency divider (FD) is designed and fabricated in a 90-nm CMOS process. With three pairs of nMOS switches inserted in the signal paths of the regenerative divider, the FD can offer three selectable division ratios of 1/2, 1/3, and 1/4. The corresponding behavior model of the proposed divider is utilized to explain the operation principle and analyze the locking ra...

This work describes the design of a divder technique Low-power techniques are applied in the design of the unit, and energy-delay tradeoffs considered. The energy dissipation in the divider can be reduced by up to 70% with respect to a standard implementation not optimized for energy, without penalizing the latency. In this dividing technique we compare the radix-8 divider is compared with one ...

A novel compact wideband (2-12 GHz) Wilkinson equal power divider on microstrip line is proposed in this paper. In this paper, a novel approach to the design of a Wideband (2-12) power divider is presented. In order to achieve the wideband performance, the divider is established by introducing variable width of microstrip line between input lines to output lines of different impedance. Finally,...

5G new spectrum radio access should support data rates exceeding 10Gbps in most of its applications. An Ultra Wide Band (UWB) Ultra-high data rate Wilkinson power divider up to 6.9Gbps for 5G new spectrum and CAR applications is presented in this paper. The step by step design procedure, optimization and implementation of this Wilkinson power divider in 20–30GHz are completely done to achieve t...

A compact fully integrated wideband six-port device composed of a suspended stripline Wilkinson power divider and three bias stripline of 3-dB quadrature directional couplers is presented. In order to integrate a six-port circuit, a multilayer circuit structure has been adopted by the via hole interconnection at the output port of the divider. The 3-dB quadrature directional coupler is composed...

This paper presents a low power 2.4-GHz fully integrated 1 MHz resolution IEEE 802.15.4 frequency synthesizer designed using 0.18um CMOS technology. An integer-N fully programmable divider employs a novel Truesingle-phase-clock (TSPC) 47/48 prescaler and a 6 bit P and S counters to provide the 1 MHz output with nearly 45% duty cycle. The PLL uses a series quadrature voltage controlled oscillato...

Received Jan 5, 2018 Revised Mar 3, 2018 Accepted Mar 20, 2018 This paper proposed three modified Wilkinson power dividers in order to achieve a size reduction and a wide bandwidth. The first structure presented the power divider using compact folded step impedance transmission lines rather than the uniform microstrip line design for operating center frequency of 3 GHz. The second structure sho...