Trends in modeling and measurements of the Soft Error Rate (SER) critical charge (Qcrit) for recent generation CMOS SOI devices are reviewed. Modeling and measurements as a function of voltage on 65, 45, 32 and 22 nm planar, SOI devices will be presented. The modeling techniques used will be reviewed and, where possible, compared to experimental measurements. Finally modeling of new device stru...

An effective approach based on a multi-parameter rational fitting technique is proposed to model the microwave small-signal response of active solid-state devices. The model is identified by fitting multibias scattering-parameter measurements and its analytical expression is implemented in a commercial microwave circuit simulator. The approach has been applied to the modelling of a silicon-base...

This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor’s architecture is going fully depleted and its size is becoming much smaller, 28-nm and above. Reliability tests of those alternatives are first discussed. Then, a comparison is made between the two al...

This paper analyses the electrical characteristics of 10 nm tri-gate (TG) N- and P-channel silicon-on-insulator (SOI) FinFETs with hafnium oxide gate dielectric. The analysis has been performed through simulations by using Silvaco ATLAS TCAD Bohm quantum potential (BQP) algorithm. influence geometrical parameters on threshold voltage VTH, subthreshold swing (SS), transconductance on/off current...

This white paper examines three categories of process characteristics, relates them to the internal structure of modern FPGAs, and then, in turn, looks at the impact the FPGAs have on the systems that employ them. In particular, a focus on the deployment of so-called FinFET transistors shows how Altera is exploiting Intel’s 14 nm Tri-Gate process to achieve a level of FPGA density, performance,...

The emergence of fin-shaped field effect transistors (FinFETs) was governed by the requirement VLSI industry to include more functionalities per unit chip area. Enhanced gate control in a FinFET due surrounding architecture built on fundamental geometry MOSFET made them highly compatible existing CMOS circuit applications. announcement vertically stacked multiple structure named as Ribbon-FET I...