This project proposes delay efficient architecture for shift registers by using pulsed latches instead of flip flops. By using latches instead of flip-flops the major factors area and power can be reduced. By considering the necessary delays in pulses for latches the timing problem latches can be reduced. For obtaining these delays counter has to incremented by 1. The proposed kogge stone adder...

The digital hardware implementation of various fuzzy operations furthermore of fuzzy flip-flops has been the subject of intense study and application. The fuzzy D flip-flop derived from fuzzy J-K one is a single input single output unit with sigmoid transfer characteristics in some particular cases, proper to use as neuron in a Fuzzy Neural Networks (FNN). In this paper we propose the hardware ...

As the density and operating speed of CMOS VLSI chips increases, leakage power dissipation becomes more and more significant. This paper presents a leakage power behavior in Pulse triggered flip-flop. All the designs are simulated with and without the application of leakage reduction techniques and the readings are presented. By analyzing the leakage path of flip flops we propose a method to re...