This paper presents a fast and effective approach to cell-type selection and Vth assignment. In our approach, initially a solution without slew and load violation is generated. Then, the Lagrangian Relaxation considering delay sensitivities is used to reduce leakage power keeping the circuit without violations. If the set of cell-types given by Lagrangian Relaxation produces a circuit with nega...

In this paper, we consider an Airport Gate Assignment Problem that dynamically assigns airport gates to scheduled ights based on passengers' daily origin and destination ow data. The objective of the problem is to minimize the overall connection times that passengers walk to catch their connection ights. We formulate this problem as a mixed 0-1 quadratic integer programming problem and then ref...

Leakage current is a key factor in IC power consumption even in the active operating mode. We investigate the simultaneous optimization of gate size and threshold voltage to reduce leakage power. We assume a standard-cell-based design flow where the available cell sizes and threshold voltages (V t 's) are given, and model the optimization as a mixed-integer linear programming (MLP) problem. In ...

One of the basic combinatorial optimization problems is the assignment problem that deals with assigning jobs to individuals. In traditional assignment problems, n jobs usually assign to n individuals such that the total cost is minimized or the total profit is maximized. However, in numerous real-life applications, various attributes could be considered in assignment problems while data (obj...

In most libraries, gate parameters such as the pin-to-pin intrinsic delays, load-dependent coefficients, and input pin capacitances have different values for rising and falling signals. Most performance optimization algorithms, however, assume a single value for each parameter. It is known that under the load-independent delay model, the gate assignment (or resizing) problem is solvable in time...

In a hardware emulator consisting of multiple fieldprogrammable gate arrays (FPGA’s), the utilization of the FPGA logic resource is usually very low due to the limitation on the number of I/O pins. Virtual wire technology not only increases the inter-FPGA communication capability, but it also increases the logic resource utilization by means of time division multiplexing (TDM). TDM allows one p...

In this work, the design and analysis of new Level Shifter with Gate Driver for Li-Ion battery charger is proposed for high speed and low area in 180nm CMOS technology. The new proposed level shifter is used to raise the voltage level and significantly reduces transfer delay 1.3ns (transfer delay of conventional level shifter) to 0.15ns with the same input signal. Also, the level shifter with g...

quantum-dot cellular automaton (qca) is a novel nanotechnology with a very different computational method in compared with cmos, whereas placement of electrons in cells indicates digital information. this nanotechnology with specifications such as fast speed, high parallel processing, small area, low power consumption and higher switching frequency becomes a promising candidate for cmos technol...

flow regime in dam's bottom outlet is divided in pressurized flow and free surface flow by the gate located for discharge control. down stream tunnel involves high velocity multi component air –water flow studied by mathematical model. in this research work, we used finite volume mixture two phase flow model. because of high reynolds number, standard two equations k-e turbulence model was ...