The characteristics of a typical 70nm high K gate dielectrics MOSFET with different source/drain structure including S/D lift-up structure are simulated by two dimensional device simulator. The impact of FIBL effect the gate dielectric permikttivity increasing to the characteristics of MOSFET is investigated. The simulation results shows that the degradation of MOSFET characteristics can be sup...

When pushing the gate dielectric thickness of metal-oxide-semiconductor (MOS) devices down to the subnanometer scale, the most challenging issue is the interface. The interfacial transition layers between the high-k dielectric/Si and between the high-k dielectric/gate metal become the critical constraints for the smallest achievable film thickness. This work presents a detailed study on the int...

Controlling thickness and composition of gate stack layers in logic and memory devices is critical to ensure transistor performance meets requirements, especially at 10nm node due to the 3-d geometry of devices and tight process budget. It has become necessary to measure and control each layer in the gate stack before and after dielectric and metal gate deposition sequences. A typical gate stac...

Conventional scaling of gate oxide thickness, source/drain extension (SDE), junction depths, and gate lengths have enabled MOS gate dimensions to be reduced from 10μm in the 1970’s to a present day size of 0.1μm. To enable transistor scaling into the 21 century, new solutions such as high dielectric constant materials for gate insulation and shallow, ultra low resistivity junctions need to be d...

SiON/Ta2O5 stacked gate dielectric exhibits 3-5 orders smaller leakage current than SiO2 at 1.8nm, while the transistor characteristics such as mobility, Id-Vg, and Id-Vd, are similar to those of SiO2 transistor. N-channel MOSFET with equivalent SiO2 thickness down to 1.8nm (1.4nm equivalent due to elimination of poly-Si depletion) is demonstrated. Process effects are also studied for optimum p...

In this letter, the characteristics of positive bias temperature instability (PBTI) and hot carrier stress (HCS) for the lowtemperature poly-Si thin-film transistors (LTPS-TFTs) with HfO2 gate dielectric are well investigated for the first time. Under room temperature stress condition, the PBTI shows a more serious degradation than does HCS, indicating that the gate bias stress would dominate t...

The influence of processing parameters of aluminum oxide (Al2O3) and lanthanum oxide (La2O3) gate dielectric is investigated. Trimethylaluminum (TMA) and tris(isopropylcyclopentadienyl) lanthanum [La(iPrCp)3] were used as precursors separately, and H2O was used as oxidant. The ultra-thin La1 - x Al x O3 gate dielectric films are deposited on p-type silicon substrates by atom layer deposition (A...

The electrical characteristics of germanium p-metal– oxide–semiconductor (p-MOS) capacitor and p-MOS field-effect transistor (FET) with a stack gate dielectric of HfO2/TaOxNy are investigated. Experimental results show that MOS devices exhibit much lower gate leakage current than MOS devices with only HfO2 as gate dielectric, good interface properties, good transistor characteristics, and about...

An all-organic memory device based on a copper phthalocyanine (CuPc) thin-film transistor (TFT) using gold nanocrystals embedded in a polyimide gate dielectric is demonstrated. Both the gate dielectric and the active semiconductor layer are organic materials. Discrete gold nanocrystals are adopted as the charge storage medium. Under proper gate bias, gold nanocrystals are charged and discharged...

Gate-leakage reduction is the key motivation for the replacement of SiO2 with alternative gate dielectrics. 45nm gate length scaled grooved and bulk nMOSFETs are evaluated to bring out the most compatible and power saving dielectric option using Si3N4 and SiO2 using Silvaco ATLAS device simulator. At the scaled thickness, SiO2 controls the leakage better than Si3N4, whereas at increased thickne...