There are two types of field-effect transistors, the Junction Field-Effect Transistor (JFET) and the “Metal-Oxide Semiconductor” Field-Effect Transistor (MOSFET), or Insulated-Gate Field-Effect Transistor (IGFET). The principles on which these devices operate (current controlled by an electric field) are very similar — the primary difference being in the methods by which the control element is ...

The effects of gate dielectrics material in organic thin film transistors (OTFTs) were investigated. The gate dielectrics were deposited by plasma enhanced chemical vapor deposition (PECVD) with cyclohexane and tetraethylorthosilane (TEOS) respectively used as organic and inorganic precursors. The gate dielectrics (gate insulators) were deposited as either organic plasma-polymer or organic–inor...

−A 3-Transistor cell CMOS OTP ROM array using standard CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high voltage (HV) blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed struct...

We propose and analyze a novel dual-gate Spin Field Effect Transistor (SpinFET) with half-metallic ferromagnetic source and drain contacts. The transistor has two gate pads that can be biased independently. It can be switched ON or OFF with a few mV change in the differential bias between the two pads, resulting in extremely low dynamic power dissipation during switching. The ratio of ON to OFF...

High-quality single crystal diamond has been used to demonstrate the RF performance of hydrogenterminated diamond field effect transistors of varying gate lengths; this includes the first data on a sub100nm diamond transistor. The RF performance for 220nm, 120nm and 50nm gate length transistors was extracted and a cut-off frequency of 55 GHz was measured for the 50nm device. This is the highest...

The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offer different delays for different input-output paths through it, is known as a v ̄ ariable input dela...

Single-electron transistors SETs are often discussed as elements. A single-electron transistor consists of a small conducting island coupled to source and.Single-electron transistor SET is a key element in our research field where. Figure 2: Transfer of electrons is a one-by-one in Single Electron Transistor.Nanoelectronics Single-electron transistor Coulomb blockade, Coulomb. Single Electron T...

A novel reconfigurable hybrid single electron transistor/MOSFET (SETMOS) circuit architecture, namely, reconfigurable pseudo-NMOS-like logic is proposed. Based on the hybrid SETMOS inverter/buffer circuit cell, reconfigurable pseudo-NMOS-like logics that can work normally at room temperature are constructed. This kind of reconfigurable logic can implement up to 2n sorts of functions at n inputs...

A 3-transistor non-volatile analog storage cell with 14 bits effective resolution and railto-rail buffered voltage output is presented. The memory, which consists of charge stored on a MOS transistor floating gate, is written by means of hotelectron injection and erased by means of gate oxide tunneling. The circuit allows simultaneous memory reading and writing; by writing the memory under feed...

A novel diagnosis technology based on transistor operating point analysis is presented. This technology is the way to detect penetration current net result from fault, replace the net with impedance net, calculate voltage value of each node of the impedance net by OHM’s low, and then sequentially trace the fault logic propagation. The impedance is determined by using transistor dimension and it...