We present a syntactic theory for the behavioral subset of the Verilog Hardware Description Language. Due to the complexity of the language, the construction of this theory represents a serious test of the suitability of syntactic operational techniques for reasoning about industrial languages. Overall, we have found that these techniques are rather robust but with a few caveats. Our theory for...

A simple formal semantics for the standard hardware description language vhdl is set out in functional style. The presentation comprises an executable speci-cation for a synchronously clocked vhdl simulator.

When designing hardware systems, a variety of models and languages are available whose aim is to manage complexity by allowing specification of such systems at different abstraction levels. Languages such as Verilog and VHDL where designed with simulation in mind rather than synthesis and lack features such as parametrised complex circuit definitions, a must for the design of generic complex sy...

Reconfigurable computing is not anew concept but can potentially become a new phenomenon. Technological obstacles are limiting the performance of single CPUs. It is becoming apparent that hardware code acceleration will soon become the norm rather than the exception. While FPGA-based hardware accelerators have repeatedly been demonstrated as a viable option for faster computing with very large ...

The aim of this talk is to present a general framework for compiling Constraint Handling Rules (CHR) to a low level hardware description language (HDL). The benefit introduced by a CHR based hardware synthesis is twofold: it increases the abstraction level of the common synthesis work-flow and it can give significant speed up to the execution of a CHR program. I will describe a practical method...

With the growing trend in ASIC design to include more analog functions on chip, various design support and automation efforts have arisen to address the analog design concerns. Existing hardware description languages have been widely used for design representation, documentation and transfer mainly in the digital domain, with standards such as VHDL being fairly mature. In this paper we present ...

We describe a comparison of several existing hardware description languages to determine their advantages and disadvantages with regards to abstraction, code reuse, and usability. To make this comparison we will implement a FIR-filter and a FIFO-queue in every language and evaluate the result according to these criteria. The languages that will be compared are VHDL, CλaSH, Kansas Lava and MyHDL.

BLIF is a hardware description language designed for the hierarchical description of sequential circuits. We give a denotational semantics for BLIF-MV, a popular dialect of BLIF, that interprets hardware descriptions in WS1S, the weak monadic second-order logic of one successor. We show how, using a decision procedure for WS1S, our semantics provides a simple but effective basis for diverse kin...

We describe in this work a Core Generator for Pattern Recognition tasks. This tool is able to generate, according to user requirements, the hardware description of a digital architecture, which implements a Support Vector Machine, one of the current state–of– the–art algorithms for pattern recognition. The output of the Core Generator consists of a high–level language hardware core description,...

Hardware description languages hdls are a notation to describe behavioural and structural aspects of circuit designs We discuss why it is worthwhile to give a formal semantics for an hdl and why we have encoded such a semantics in a proof system We outline the subset of the hardware description language ella which we use its formal structural operational semantics and its embedding in the highe...