New middleware is proposed to support the development of dependable distributed real-time systems for avionics, sensor and shipboard computing. Many of these systems require distributed computing in order to perform increasingly complex missions. They also require real-time performance, dependable software, and may face constraints that limit hardware redundancy. Real-time performance and fault...

The purpose of this paper is twofold: we first present a novel architecture for real-time active vision systems, and then enhance the architecture with a un$ed approach to fault tolerance. Our system is designed modularly in order to enable the flexible addition of hardware and sojiware redundancy and also to allow reconfiguration when and where needed. This gives us the ability to handle fault...

This paper presents a new approach for block based motion estimation based on Boolean matching in precoded image planes. It is proposed to add redundancy to the pixel representation for the purpose of motion estimation computation reduction. Images are pre-coded lo enable a Boolean-only matching criterion that approximates the mean absolute difference. Fast matching criteria evaluation with a s...

This work addresses the problem of failure tolerance for realtime applications. We propose a technique to schedule a system of tasks running under PD2 on a multicore architecture submitted to the failure of one of the cores at a given time with re-execution of the task running on it. The technique is based on limited hardware redundancy and subtask feasibility windows reconfiguration at runtime...

• FIB aggregation • Reduce the size of the Forwarding Information Base (FIB) • Remove redundancy while ensuring forwarding consistency with the original FIB • Traffic offloading • Glue together a hardware-centric forwarding fabric (fast-path) with a softwarecentric route controller (slow-path) • Offload the top-volume FIB entries to the fast-path, handle the remainder at the slow-path • Leverag...

This paper presents a low-cost approach to concurrent error correction in high-performance CORDIC processors by using time-shared triple modular redundancy. Operands are partitioned into three sets of disjoint digits and operations are performed three times on different hardware components to correct possible errors by majority voting. The approach has limited latency increase and throughput re...

An improvement of the majority gate algorithm suitable for grey scale morphological operations is presented in this letter. The redundancy of temporal signals led to a simplified hardware implementation. It is shown that max/min operators can be computed by the same circuit. A new pipelined systolic array architecture based on this circuit is illustrated for dilation/erosion operations. 2 Intro...

This paper presents an on-line self-test architecture for hardware implementation of the Advanced Encryption Standard (AES). The solution exploits the inherent spatial replications of a parallel architecture for implementing functional redundancy at low cost. We show that the solution is very effective for on-line fault detection while keeping the area overhead very low. Moreover, the architect...

Creating diverse redundancy for fail safe or fail operational systems in software reduces costs for additional hardware and increases flexibility. A lack of performance occurs by implementing a diverse software channel for e.g. floating-point operations in a traditionally microcontroller architecture. This paper gives an approach for transferring the Safely Embedded Software (SES) into a coproc...

This paper presents a method of using hardware redundancy to ease the problem of fault testing in combinational logic networks. Combinational logic networks are constructed using dual-mode logic gates. Initially, it is shown that these networks can be tested for all single stuck-at-faults using just two function-independent tests. This method is then extended to detect a large class of multiple...