In this paper a new CMOS current-mode four-quadrant analog multiplier and divider circuit based on squarer circuit is proposed. The dual translinear loop is the basic building block in realization scheme. Supply voltage is 3.3V. The major advantages of this multiplier are high speed, low power, high linearity and less dc offset error. The circuit is designed and simulated using HSPICE simulator...

In this paper, we provide an analytical framework to study the inter-cell and intra-cell bit-line coupling when it is superimposed with the ground bounce effect and show how those noises impair the performance of SRAM. The impact of noises is expressed in term of a coupling noise degradation factor and a ground bounce degradation factor. We have used analytical techniques to reduce the governin...

In this paper we present an ultra low-voltage and high speed D flip-flop. The flip-flop has an increased current level compared to standard CMOS circuits operating at low supply voltages. The increased current level is obtained by using a synchronized capacitive coupling to a semi floating-gate. The delay of the static differential flip-flop presented is less than 12% compared to conventional d...

This paper presents two new general threshold gate (GTG) structures which are based on the monostable-bistable element (MOBILE) as their main part. These new GTGs eliminate an RTD from the structure compared to old structures and lead to less elements count and better performance in terms of power consumption, maximum frequency, and power-delay product (PDP). In the paper also two new single ga...

With deep submicron technology nodes other methods are needed to obtain scaling factors rather than the traditional scaling factors which held for the pre-submicron era. This work presents scaling factors between major technology nodes between 180 nm and 22 nm operating at voltages from 1.8 V to 0.7 V. Common operating data for these technologies were taken from the International Technology Roa...

Addition is the fundamental operation for any VLSI processors or digital signal processing. In this paper focuses on carry -look ahead adders have done research on the design of high-speed, low-area, or low-power adders. Here domino logic is used for implementation and simulation of 128 bit Carrylook ahead adder based HSPICE Tool. In adder circuits propagation delay is the main drawback. To ove...

The focus of this paper is that the coming up with of TCAM using Master Slave Match Line style. Typically CAM may be a memory that has parallel comparison feature used in quick hunt applications. Attributable to this feature massive power consumption takes place in CAM. Thus a brand new design known as MSML style is projected which mixes the master – slave design and charge refill minimization ...

Non zero signal rise and fall times contribute significantly to CMOS gate performances such as propagation delay or short circuit power dissipation. We present a closed form expression to model output rise and fall times in deep submicron CMOS structures. The model is first developed for inverters considering fast and slow input ramp conditions. It is then extended to gates through a reduction ...

A new Successive-Approximation ADC (Analog-toDigital Converter) was designed which not only consumes little power, but also requires a small chip area. To achieve those goals, both comparator and internal DAC (Digital-to-Analog Converter) have been improved. The ADC was designed in a 1.2 μm CMOS double-poly double-metal n-well process. It performs 10-bit conversion with 67 dB SFDR. Power consum...

CNFET is generally considered to be one of the most appealing next generation transistors because of its high current carrying capacity and ballistic transport property. This paper investigates the performance analysis of Dual-X Current Conveyor with the CNFET technology, by varying the CNT diameter at 32nm technology node. Current Bandwidth, Input and Output Port resistances of the device alon...