نتایج جستجو برای: large scale integration
تعداد نتایج: 1584820 فیلتر نتایج به سال:
At the core of contemporary VLSI designs is the task of determing and evaluating the set of decisions relevant for the particular design project. In many designs the set of design decisions is handled intuitively, and also the set of alternatives for each of the design decisions is strongly influenced by experiences from earlier designs. The paper discusses the list of design decisions under co...
This chapter presents a brief overview of some of the major research contributions in the area of VLSI computing with optical interconnects since the early modelings of the 1980s to today’s MEMS implementations. Both free-space and fiber-guided interconnects are covered. Various models and architectures with optical interconnects are shown, and aspects of their algorithmic design are also revie...
This paper discusses recently introduced strategies in implementing DSP systems using residue replication; in particular we highlight current work underway in the VLSI Research Group, at the University of Windsor, in the area of constructing high throughput DSP systems on silicon. The paper first briefly reviews the theory and mapping techniques, associated with general residue and residue repl...
Now, we come to offer you the right catalogues of book to open. applications of finite element methods for reliability studies on ulsi interconnections is one of the literary work in this world in suitable to be reading material. That's not only this book gives reference, but also it will show you the amazing benefits of reading a book. Developing your countless minds is needed; moreover you ar...
Timing Analysis and Optimization Techniques for VLSI Circuits
The layout design to improve uniform ESD current distribution in multi-finger MOSFET devices for better ESD robustness is investigated in a 0.18-μm salicided CMOS process. The multi-finger MOSFET, without adding the pick-up guard ring inserted into its source region, or with the vertical direction of power line connection, can sustain a higher ESD level. The layout of I/O cell can be drawn more...
An area-universal VLSI circuit can be programmed to emulate every circuit of a given area, but at the cost of lower area-time performance. In particular, if a circuit with area-time bounds (A; T ) is emulated with a universal circuit with bounds (Au; Tu); we say that the universal circuit has blowup Au=A and slowdown Tu=T . A central question in VLSI theory is to investigate the inherent costs ...
viiiAcknowledgments, vBibliography, 295Conclusion, 257Dedication, ivDesign Closure, 6Emerging Technologies, 197Introduction, 1Manufacturing Closure, 110
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