(VCO) phase-locked loop (PLL) and ring-VCO PLL topologies with low-phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer-resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out-band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65-nm or 45-nm process. The measured resu...

In grid-connected inverters (GCIs), the phase-locked loop (PLL) behaves as a negative admittance at point of common coupling (PCC), composed both PLL controller and current terms. Therefore, not only dynamics, but also dynamical interactions between might trigger instabilities in weak grids, which complicates parameters regulation. The smaller bandwidth could help to mitigate instabilities, exp...

Due to a number of desirable operational and design characteristics, CP-PLL’s (Charge Pump Phase locked loops) have, in recent years become a pervasive PLL architecture. CP-PLL architectures are exploited for a variety of applications such as on chip clock generation, CRC (clock recovery circuits) and Radio frequency synthesis applications. This paper describes a simple, digital only, minimally...

Although the stability of grid-connected photovoltaics (PV) and energy storage systems under weak grids has been widely researched, classical improvement methods focus more on suppressing harmonics introduced by phase-locked loop (PLL). Furthermore, current distortion caused DC voltage is difficult to be eliminated. In this study, based hybrid system battery-supercapacitor, a dual-loop compensa...

We have developed a wideband phase-locked loop (PLL) circuit with real-time phase correction for high-speed and accurate force measurements by frequency modulation atomic force microscopy (FM-AFM) in liquid. A high-speed operation of FM-AFM requires the use of a high frequency cantilever which, however, increases frequency-dependent phase delay caused by the signal delay within the cantilever e...

Based on multi-dimensional representation and vector calculus definitions, this paper proposes two novel and quite simple algorithms for utility applications and power quality analysis. The first one is a synchronizing procedure, based on a digital PLL (Phase Locked Loop). Its design and dynamic behavior are analyzed for single and three-phase systems. The second one is a positive sequence dete...

Distributed beamforming between separate wireless nodes in a distributed antenna array requires significant coordination of the relative electrical states systems to achieve and maintain phase-coherent state. A principal factor impacting phase coherence is stability local oscillators on each node. Ensuring coherent state distribution reference frequency such that all are operating same basis fr...

This paper describes a low-jitter phase-locked loop (PLL) implemented in a 0.18m CMOS process. A sample–reset loop filter architecture is used that averages the oscillator proportional control current which provides the feedforward zero over an entire update period and hence leads to a ripple-free control signal. The ripple-free control current eliminates the need for an additional filtering po...

—For positioning with Global Navigation Satellite System (GNSS) in urban canyon area, besides the weak signal power, the satellite signal may also be frequently sheltered and no power can be received. It is a great challenge for the GNSS receiver to keep positioning continuously. If the tracking loop in GNSS receivers can recover locking the signal soon after the signal appears again, it will ...

In this paper, an adaptive version of the impedance-conditioned phase-locked loop (IC-PLL), namely IC-PLL (AIC-PLL), is proposed. The has recently been proposed to address issue synchronisation with a weak AC grid by supplementing conventional synchronous reference frame (SRF-PLL) additional virtual impedance term. resulting aims synchronise converter remote and stronger point in grid, hence in...